1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

Byun, Sangjin; Son, Chung Hwan; Hwang, Jong-Il; Min, Baehyun; Park, Mun-Yang; Yu, Hyun-Kyu

doi:10.1049/iet-cds.2013.0023

Cited by 10 publications

(3 citation statements)

References 19 publications

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“…1, the VCO has the 2b digital coarse tuning and analog fine tuning blocks. The CCO is designed with four current controlled delay cells and a replica bias circuit to generate the differential I/Q clock signals [10,11]. The VCO consumes 0.8 mA∼3.2 mA from 1.2 V core supply at 1 GHz∼3 GHz frequencies.…”

Section: Simulation Results and Conclusionmentioning

confidence: 99%

1∼3 GHz VCO with rail-to-rail V<sub>CONT</sub> range

Byun

2016

IEICE Electron. Express

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This paper presents a 1∼3 GHz voltage controlled oscillator (VCO) with a rail-to-rail VCO tuning voltage (V CONT ) range. To obtain wide and linear V CONT range, a new differential amplifier with a rail-to-rail common mode input range and an unstacked output stage is proposed. By using the proposed differential amplifier in the analog fine tuning block, V CONT can span almost the rail-to-rail supply voltage with good linearity. For verification, a prototype VCO was fabricated in a 65 nm 1P7M CMOS process.

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Section: Simulation Results and Conclusionmentioning

confidence: 99%

1∼3 GHz VCO with rail-to-rail V<sub>CONT</sub> range

Byun

2016

IEICE Electron. Express

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“…7 b shows the XOR gate with two differential input data ports. Both are implemented in a stacked CML structure for high‐speed operation [19, 20]. One difference between them is that the latch has one input data and one input clock ports while the XOR gate has two input data ports.…”

Section: Circuit Implementationmentioning

confidence: 99%

0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling

Byun

2016

IET Circuits, Devices & Systems

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This paper presents a low-power complementary metal-oxide-semiconductor (CMOS) clock and data recovery (CDR) integrated circuit (IC) with dynamic voltage scaling (DVS) technique. When DVS is adopted, the power efficiency can be improved by selecting the low supply voltage as possible for a given bit rate. However, the supply voltage generated from a switching regulator such as a buck converter has the ripple voltage at the switching frequency so that the CDR performance may be degraded accordingly. Thus, in this study, the analysis on the relationship among the ripple voltage, the switching frequency and the jitter tolerance (JTOL) is carried out and the appropriate ripple voltage and switching frequency of the buck converter are chosen based on the analysis. Moreover, low supply voltage circuit techniques are carefully utilised for the design of the low-power CDR IC. The CDR IC, implemented in a 0.11 μm CMOS process, shows the power efficiency of 0.97 mW/Gb/s at 4 Gb/s including the buck converter. When 4 Gb/s 2 31 −1 pseudorandom binary sequence is used, the measured bit error rate is better than 10 −12 , the measured JTOL is 0.3 UI pp and the measured jitter of the recovered clock is 6.1 ps rms .

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“…To cover the wide range of data rates of the clock and data recovery (CDR) loops and to compensate for the process, voltage, and temperature (PVT) variations of clock frequency from voltage controlled oscillator (VCO), various frequency acquisition techniques have been utilized [1][2][3][4][5][6][7][8][9] in the serial data interfaces. However, most of these techniques originate from the thought that the phase detectors cannot detect the frequency difference between the received data and the recovered clock in the CDR loops.…”

Section: Introductionmentioning

confidence: 99%

More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

Byun¹

2018

Electronics

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Abstract:The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under the condition that the ratio of the received data frequency (f DATA ) and the recovered clock frequency (f CLK ) is set as an integer number. In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are studied again while the ratio of f DATA and f CLK is set as a general rational number. Additionally, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop clock and data recovery (CDR) including the full-rate linear PD are newly developed and verified. The calculated lock times by the analysis results agree well with the measured lock times from the MATLAB Simulink simulations.

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1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

Cited by 10 publications

References 19 publications

1∼3 GHz VCO with rail-to-rail V<sub>CONT</sub> range

1∼3 GHz VCO with rail-to-rail V<sub>CONT</sub> range

0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling

More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

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