2016
DOI: 10.1109/access.2016.2599408
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1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

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Cited by 26 publications
(6 citation statements)
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“…Parallel hardware implementation is another important measure to reduce signal processing latency. For example, the recently proposed parallel turbo decoder architecture [14] eliminates the serial data dependencies, realizes full parallel processing, realizes full parallel processing, offers an average throughput of 1.53 Gb/s, and finally achieves a 50% hardware resource reduction compared with the original architecture.…”
Section: Ultra-fast Signal Processingmentioning
confidence: 99%
“…Parallel hardware implementation is another important measure to reduce signal processing latency. For example, the recently proposed parallel turbo decoder architecture [14] eliminates the serial data dependencies, realizes full parallel processing, realizes full parallel processing, offers an average throughput of 1.53 Gb/s, and finally achieves a 50% hardware resource reduction compared with the original architecture.…”
Section: Ultra-fast Signal Processingmentioning
confidence: 99%
“…The usage of FPGA-based systems in the telecommunication industry is widespread, with typical applications in the development of general transmission decoders [16,17], video decoders [18,19], security approaches like parity checks [20,21], satellite issues [22,23], and digital TV systems [24]. The modern usage of those devices includes machine learning proposals [25], cloud computing [26], and 5G communication networks [27].…”
Section: Related Workmentioning
confidence: 99%
“…Several works have adopted the key perspective of pushing promising algorithms from a simple software status to a fully-functional hardware prototype [17]- [19]. More than proving the concept, this perspective significantly reduces time-to-market for new outstanding application-oriented techniques.…”
Section: Fpgamentioning
confidence: 99%