2020 Advanced Computing and Communication Technologies for High Performance Applications (ACCTHPA) 2020
DOI: 10.1109/accthpa49271.2020.9213214
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1-Bit Full Adder Output Analysis Using Adiabatic ECRL Technique

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Cited by 6 publications
(1 citation statement)
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“…In digital circuits, the primary focus remains on decreasing the dynamic power consumption so as increase the battery life. A high-performance FA circuit must have low dynamic power, P D (nW), low propagation delay, T D (pS), and low power-delay product, PDP (10 −18 J) [33][34][35][36][37][38][39][40]. For the sake of comparative analysis, the previously proposed high-performance FAs have been re-designed using 16 nm SPICE-compatible GNRFET model [26] and fairly compared with proposed PPN 12 T GNRFET FA in this work.…”
Section: Introductionmentioning
confidence: 99%
“…In digital circuits, the primary focus remains on decreasing the dynamic power consumption so as increase the battery life. A high-performance FA circuit must have low dynamic power, P D (nW), low propagation delay, T D (pS), and low power-delay product, PDP (10 −18 J) [33][34][35][36][37][38][39][40]. For the sake of comparative analysis, the previously proposed high-performance FAs have been re-designed using 16 nm SPICE-compatible GNRFET model [26] and fairly compared with proposed PPN 12 T GNRFET FA in this work.…”
Section: Introductionmentioning
confidence: 99%