1/f-Noise in AlGaN/GaN Nanowire Omega-FinFETs

Vodapally, Sindhuri; Jang, Young In; Kang, In Man; Cho, In-Tak; Lee, Jong-Ho; Bae, Young Ho; Ghibaudo, G.; Cristoloveanu, S.; Im, Ki‐Sik; Lee, Jung‐Hee

doi:10.1109/led.2016.2645211

Cited by 25 publications

(15 citation statements)

References 15 publications

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“…•eV −1 for the narrow/wide Fin device [15]. This reduced N t in narrow Fin device proved to be the significant volume accumulation effect, which is similar with the volume inversion phenomenon in Si FinFETs [17].…”

Section: Introductionsupporting

confidence: 53%

“…3 d values for the device with W Fin = 20 nm are observed at subthreshold region. The reason for the lowest noise levels for the narrow Fin device at I d < 10 −5 A is because of the volume accumulation effect in the bulk channel [15], [17]. In the narrow Fin structure, the accumulated carriers in MOS channels are repelled from the interface toward the center of the body, causing the narrow Fin device to have reduced noise [15], [17].…”

Section: Characterization Results and Discussionmentioning

confidence: 99%

“…Our group has already reported on the low-frequency noise (LFN) analysis in AlGaN/GaN nanowire FinFETs in order to find the dominance of the channel conduction mechanisms (2DEG versus MOS conduction) and also calculate the trap density (N t ) [15], [16]. These fabricated Fin devices showed the carrier number fluctuations (CNF) regardless of W Fin and N t of 2.4 × 10 21 /4.3 × 10 21 cm −3…”

Section: Introductionmentioning

confidence: 99%

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Impact of Fin Width on Low-Frequency Noise in AlGaN/GaN FinFETs: Evidence for Bulk Conduction

2023

IEEE Access

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AlGaN/GaN Fin-shaped field-effect transistors (FinFETs) with nano-sized Fin width (W Fin ) from 20 nm to 230 nm are characterized using low-frequency noise (LFN) measurement. All devices exhibit 1/f noise shape with Hooge mobility fluctuations (HMF) at subthreshold region and carrier number fluctuations (CNF) at accumulation region. However, the lowest normalized drain current noise spectral densities (S Id /I 2 d ) are obtained in the narrow Fin device (W Fin = 20 nm). This is due to significant contribution of bulk channel without the 2-dimensional electron gas density (2DEG) channel and two sidewall metal-oxide-semiconductor (MOS) channels. It is also noticed that the lowest trap density (N t ) and a large separation in CNF noise model clearly indicate to the volume accumulation effect caused by bulk conduction in narrow device. The Hooge constants (α H ) extracted by HMF noise model for the narrow device are one-order higher than those of the wide Fin device, which tells that the narrow device suffers from the strong phonon scattering in the bulk channel. From the product of (S Id × frequency (f )) versus I d curves, the volume accumulation phenomenon is also clearly observed in narrow Fin device.INDEX TERMS AlGaN/GaN FinFET, fin width, low-frequency noise, bulk conduction, volume accumulation.

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Section: Introductionsupporting

confidence: 53%

Section: Characterization Results and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Impact of Fin Width on Low-Frequency Noise in AlGaN/GaN FinFETs: Evidence for Bulk Conduction

2023

IEEE Access

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“…Semiconductor fins or nanowalls (i.e., nanoribbons standing with their narrow facets on the surface, like a wall on the ground) are the building blocks for conducting channels in tri-gate FETs. To date, commercial silicon tri-gate FET fins and nanowalls of other tri-gate FETs under investigation − have been fabricated top-down. In contrast, although a few semiconductor nanowalls have been obtained via bottom-up approaches, − they have not yet been employed to build tri-gate FETs.…”

Section: Introductionmentioning

confidence: 99%

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls

Oksenberg

Popovitz‐Biro

et al. 2017

J. Am. Chem. Soc.

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Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10, 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

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“…Furthermore, the experimental study carried out with/without heterojunction GaN FinFET manifests that as the fin width is reduced, threshold voltage shifts towards positive direction [3]. The low frequency noise (LFN) characteristics are investigated for GaN based FinFET having an omega shaped gate and demonstrated that LFN is independent of the width of the fin [5]. Moreover, T-shaped gate GaN FinFET shows linear transconductance and superior power performance [6].…”

Section: Introductionmentioning

confidence: 99%

Analysis of GaN nanoscale FinFET for low power circuit applications

Das

Baishya

2018

Micro & Nano Letters

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This work introduces a structure of GaN FinFET at the nanoscale (channel length L = 5 nm) and characterises its performance in low power circuit applications. The simulated outcomes justify its application in circuits having I ON , I OFF , and I ON /I OFF of the order of 10 −3 A, 10 −13 A, and 10 10 A, respectively, with quality factor Q = 1.11 × 10 −5 S-dec/mV computed at I OFF 10 −13 A and V DS = 0.5 V. The measured observations are compared with other materials and we observed significant improvement, of the orders of 1 in the case of I ON and 3 in the case of I OFF ; while the same for the Q witnesses a growth of 42%, especially with respect to silicon. The prospect of the proposed device architecture has also been investigated by implementing it in the digital circuits such as the inverter and universal logic gates (NAND and NOR gates), where it showed improved performance like high gain and absence of overshoot and undershoot in the switching characteristics.

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1/f-Noise in AlGaN/GaN Nanowire Omega-FinFETs

Cited by 25 publications

References 15 publications

Impact of Fin Width on Low-Frequency Noise in AlGaN/GaN FinFETs: Evidence for Bulk Conduction

Impact of Fin Width on Low-Frequency Noise in AlGaN/GaN FinFETs: Evidence for Bulk Conduction

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls

Analysis of GaN nanoscale FinFET for low power circuit applications

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