A digital-to-analogue multiplier based on the principle of passive charge sharing and redistribution is proposed. The circuit generates a voltage proportional to the multiplier, then samples this voltage with a capacitance proportional to the multiplicand by discharging the capacitance associated with its logical inverse. Parasitic capacitances are shown to result in an input-referred offset with respect to the multiplier. The switching scheme is modified to null the offset. Simulation results are provided to verify the operation of the digital-to-analogue multiplier.Introduction: A number of machine learning applications are amenable to approximate computing [1]. With the complexity of modern machine learning systems growing rapidly [2], approximate computing promises to deliver the energy savings necessary to deploy trained systems in practical applications.It has been shown in [3] that analogue circuits can perform with greater power efficiency than digital circuits in low precision signal processing. However, the massive scale of modern machine learning systems favours circuits that reside in a digital very large-scale integration environment, with digital input/output interfaces. Several designs fulfilling these properties have been proposed [4,5], but they fell victim to the digital alternatives which benefited from rapid CMOS scaling occurring at the time. With the performance improvement rate of digital CMOS slowing down, there now exists a renewed interest in mixed-signal circuits for approximate computing [6].Switches and capacitors as signal processing elements are well-suited to ultimately scale CMOS. A switched-capacitor multiplier/divider has been proposed [7], but it contains amplifiers -a significant source of static power dissipation. This Letter describes a passive charge redistribution digital-to-analogue multiplier based on the charge-domain techniques in [8], with the goal of improving the energy-efficiency of the multiplier block in a mixed-signal computing system.