IEEE Trans. Circuits Syst. II
 2013
DOI: 10.1109/tcsii.2013.2258255
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12.5-Gb/s Full-Rate CDR With Wideband Quadrature Phase Shifting in Data Path

Arash Zargaran-Yazd
1
,
Shahriar Mirabbasi
2
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Cited by 5 publications
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References 13 publications
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Discrete-time modeling and simulation considerations for high-speed serial links

Zargaran-Yazd
1
,
Beyene
2
2014
2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems
2
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0
0
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Discrete-time modeling and simulation considerations for high-speed serial links

Zargaran-Yazd
1
,
Beyene
2
2014
2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems
2
0
0
0
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A 10 Gbps SerDes for wireless chip-to-chip communication

Han
1
,
Kim
2
,
Kim
3
et al. 2015
2015 International SoC Design Conference (ISOCC)
7
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An Odd Phase CDR With Phase Interpolator Trimming

Joshi
1
,
Sarkar
2
2019
IEEE Trans. Circuits Syst. II
7
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