128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode

Li, Yan; Lee, Seungpil; Oowada, K.; Nguyen, Hao; Nguyen, Qui; Nima, Mokhlesi; Hsu, Cynthia; Li, Jason; Ramachandra, Venky; Kamei, Takeshi; Higashitani, M.; Pham, T.; Honma, Mareki; Watanabe, Yoshihisa; Ino, K.; Le, Binh; Woo, B.J.; Htoo, Khin; Tseng, Tsun-Ming; Pham, Long; Tsai, Frank C.; Kim, Kwang‐Ho; Chen, Yi-Chieh; She, Min; Yuh, J.; Alex, Chu; Chen, Chen; Puri, Ruchi; Lin, Hongwei; Chen, Yifang; William, Mak; Huynh, Jonathan; Chan, Jennifer; Watanabe, Mitsuyuki; Yang, Daniel; Grishma, Shah; Souriraj, Pavithra; Dinesh, Tadepalli; Suman, Tenugu; Ray, G. P.; Popuri, Viski; Azarbayjani, Behdad; Madpur, Ravindra; Lan, J.; Yero, E.; Pan, Feng; Patrick, Hong; Kang, Jang Yong; Moogat, Farookh; Fong, Y.; Cernea, Raul; Huynh, Sharon; Trinh, Cuong; Mofidi, M.; Shrivastava, Ritu; Quader, K.

doi:10.1109/isscc.2012.6177080

Cited by 17 publications

(9 citation statements)

References 5 publications

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“…A good overview of EEPROM/Flash history was presented at ISSCC2012 (Harari, 2012). Recent data on EEPROM devices shows commercially announced devices at 15 nm (Hynix, IEDM) and 19 nm [Toshiba/ScanDisk (Li et al, 2012; Shibata et al, 2012) and Samsung (Lee et al, 2012)] as well as production of 32 nm devices. From the current EEPROM progress, such devices are expected to migrate to 7 and 11 nm technology nodes; therefore the risk that the industry will not commercially produce a 10 nm floating-gate device is very low.…”

Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

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Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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“…On the contrary NAND Flash evolution in the last decade has shown an impressive growth rate of a factor or 3Â/year in terms of MB/cm 2 . For NAND Flash this evolution has essentially been achieved by the wide adoption of multi-bit storage, reaching the level of 3 bit/cell for 20 nm technology node [4,5]. Very sophisticated design solutions have been put in place to overcome all problems related to cell to cell electrostatic interference, read disturbs and cycling defects.…”

Section: Evolution Of Mainstream Memorymentioning

confidence: 99%

Emerging memories

Baldi

Bez

Sandhu

2014

Solid-State Electronics

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a b s t r a c tMemory is a key component of any data processing system. Following the classical Turing machine approach, memories hold both the data to be processed and the rules for processing them. In the history of microelectronics, the distinction has been rather between working memory, which is exemplified by DRAM, and storage memory, exemplified by NAND. These two types of memory devices now represent 90% of all memory market and 25% of the total semiconductor market, and have been the technology drivers in the last decades. Even if radically different in characteristics, they are however based on the same storage mechanism: charge storage, and this mechanism seems to be near to reaching its physical limits. The search for new alternative memory approaches, based on more scalable mechanisms, has therefore gained new momentum. The status of incumbent memory technologies and their scaling limitations will be discussed. Emerging memory technologies will be analyzed, starting from the ones that are already present for niche applications, and which are getting new attention, thanks to recent technology breakthroughs. Maturity level, physical limitations and potential for scaling will be compared to existing memories. At the end the possible future composition of memory systems will be discussed.

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“…4 At the 2012 International Solid-State Circuits Conference, SanDisk reported on the development of a 128-Gbit X3 with 18-MBps write performance. 5 These additional improvements in X3 NAND flash write performance will reduce cost sufficiently to satisfy client applications.…”

Section: Architectural Improvementsmentioning

confidence: 99%

“…10 SanDisk used a similar algorithm in 19-nm X3 NAND flash to reduce cell-to-cell coupling by up to 95 percent. 5 The drawback of multiple-pass programming is that the controller must retain more data in the controller RAM before releasing the buffer for future data.…”

Section: Less Cell-to-cell Interferencementioning

confidence: 99%

NAND Flash Memory: Challenges and Opportunities

Li¹,

Quader²

2013

Computer

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NAND flash offers a range of compelling benefits that will keep attracting mobile and enterprise application developers as engineers tackle the hard problems of scaling the technology to sub-20 nm.S ince NAND flash entered the market in 1987, its relatively low cost, compact size, quiet operation, speed, and ruggedness have made it a popular choice for mobile platforms such as smartphones and tablets, and it is replacing hard drives in many client and enterprise applications.In recent years, developers have successfully scaled 2D NAND flash to sub-20-nm technology, but further 2D NAND scalability will be a considerable challenge. Although new alternatives, such as 3D resistive RAM (ReRAM), are aiming to replace 2D NAND flash, NAND's entrenched position among nonvolatile storage options and the attractiveness of its low power consumption will make flash technology difficult to unseat. In enterprise storage, for example, flash solid-state drive (SSD) architectures are already leveraging massive parallelism to deliver high I/O operations per second for less power and cost than any currently available and practical technology.With these strong advantages, NAND can potentially supplant a portion of the dynamic RAM (DRAM) market, 1 and we expect future computing platforms to maximize NAND flash use in mobile, enterprise, and client product designs. Indeed, Gartner has forecast that units in all applications will triple over the next five years, with an average fourfold to fivefold capacity increase in SSDs over the same period. 2 The widespread adoption of flash will drive deeper cost reductions, which manufacturers will realize through increased scaling. As NAND flash devices scale down, application-specific systems management must maintain product reliability while continuing to address reduced endurance.Maintaining the reliability of NAND flash at 19 nm and beyond will also require breakthrough memory and system algorithms. Many efforts are in progress on more innovations in memory architecture, reliability, power, and high-speed I/O interfaces. Another body of work is focusing on the system design challenges of scaling 2D NAND flash, offering 3D NAND and other novel technologies as possible solutions. ArchitecturAl improvementsFor many years, half-bit-line (HBL), or shielded bit-line, architecture was the conventional NAND architecture in which, as Figure 1 shows, the system reads or writes only half the cells at a time to the word line. In 2008, SanDisk introduced all-bit-line (ABL) architecture, 3 which uses a current-sensing scheme to connect each bit line to the sensing amplifier and a set of data latches.ABL was a considerable improvement over HBL. In addition to doubling read and write throughput, ABL architecture has intrinsically better reliability. In HBL architecture, reading or programming stresses the same word line twice with high voltages; in ABL architecture, writing the same number of cells stresses the word line only once. The doubled high-voltage stress during program and read operations worsens m...

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128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode

Cited by 17 publications

References 5 publications

Finding a roadmap to achieve large neuromorphic hardware systems

Finding a roadmap to achieve large neuromorphic hardware systems

Emerging memories

NAND Flash Memory: Challenges and Opportunities

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