13.56 MHz CMOS transceiver for RFID applications

Meillere, S.; Barthélémy, H.; Martin, Michel

doi:10.1007/s10470-006-0392-8

Cited by 16 publications

(8 citation statements)

References 7 publications

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“…The system in [8] with the ASK demodulation achieves a higher data rate, but the higher supply voltage causes higher power consumption. Moreover, the core area of 0.373 mm 2 is larger than those of other publications.…”

Section: Resultsmentioning

confidence: 99%

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PLL-Based Contactless Energy Transfer Analog FSK Demodulator Using High-Efficiency Rectifier

Hwang

Lin

et al. 2013

IEEE Trans. Ind. Electron.

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This paper proposes a new phase-locked-loop (PLL)-based inductive coupled contactless energy transfer (CET) analog frequency-shift keying (FSK) demodulator using a high-efficiency RF-to-dc rectifier for biomedical implanted devices. The analog FSK demodulator is composed of a modified CMOS three-stage rectifier, a voltage regulator, an FSK signal generator, and a PLL. The proposed modified single-stage rectifier with both positive and negative output voltages using a PMOS and an NMOS pass transistor, an inverter, and two capacitors has a small active area and can enhance the power conversion efficiency. The proposed RF-to-dc rectifier achieves an efficiency of 64% at 8.4 dBm. The power consumption of the demodulator is as low as 0.76 mW, and the active area is 0.084 mm 2 . The analog FSK demodulator supports a data rate of 100 kb/s to 1 Mb/s. The chip was implemented in a Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-μm double-poly quadruple-metal CMOS technology to verify the proposed CET circuit. Two figures of merit are provided to illustrate the advantages of the proposed architecture. Index Terms-Contactless energy transfer (CET), frequencyshift keying (FSK) demodulator, phase-locked loop (PLL), power conversion efficiency, rectifier.

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Section: Resultsmentioning

confidence: 99%

“…The inverter-driven comparator in [8] and the voltage-controlled ring OSC in [9] might cause the increase of ground bounce. The digital-mode FSK demodulator in [27] requires the high-speed clock frequency; the ground bounce will be increased.…”

Section: Resultsmentioning

confidence: 99%

PLL-Based Contactless Energy Transfer Analog FSK Demodulator Using High-Efficiency Rectifier

Hwang

Lin

et al. 2013

IEEE Trans. Ind. Electron.

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“…Nowadays, the wireless power transfer is being widely accepted in electronic implementations to improve device reliability and to extend battery life. These implementations mainly include wireless sensor networks (WSN) [2,3], radio frequency identification (RFID) [4,5] tags and smart biomedical devices [6,7]. The block diagram of a typical wireless power transfer mechanism is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A complete analysis and measurement results of the threshold voltage cancellation scheme for RF to DC converter

Chouhan

Halonen

2015

Analog Integr Circ Sig Process

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In this work, the threshold voltage cancellation scheme for the RF-to-DC converter used in RF energy harvesting is presented. The proposed scheme reduces the threshold voltage of PMOS transistor used in CMOS rectifier with the use of additional CMOS components. The performance of the proposed scheme is evaluated against the conventional CMOS rectifier in terms of the power conversion efficiency (PCE). Measurements were done at 433 MHz RF frequency for resistive load values ranging from 1 to 120 KX. The measured peak PCE of the conventional CMOS and proposed rectifiers are 16 and 35 %, respectively, for the input RF power level of À8 dBm and resistive load of value 10 KX. The implementation of the proposed scheme is also tested in the multi-stage rectifier circuit (MSC) topology. All PMOS-based DTMOS-biased MSC circuit was selected to implement the proposed scheme and for performance comparison. The measured results show the PCE of a five stage DTMOS-biased MSC circuit is 15 % @ À6 dBm with 66 KX resistive load whereas after implementing proposed scheme on the alternate PMOS transistors of DTMOS-biased MSC circuit resulted into 19 % PCE for the same input and output conditions.

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“…Designs reported by Dong et al [6] and Sawan et al [7] are companionable upto 10 MHz and 13.56 MHz respectively; To obtain compatibility at 13.56 MHz, Sawan et al [7] used large number of MOSFETS. Meillere et al [8] showed the design of a demodulation system, which has frequency compatibility with ISO/IEC 14443 standardization and the power cunsumption is relatively high. Systems deliniated by Alegre et al [9]show less ripple and faster settling time at 10 MHz frequency.…”

Section: Introductionmentioning

confidence: 99%

A Low Ripple Low Power CMOS Demodulator for 13.56 MHz RFID Reader

Karim¹,

Ali²,

Reaz³

et al. 2010

Frequenz

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This study concerns about a high frequency spectrum companionable CMOS demodulator design for RFID application. In this paper,implementation of a demodulator is described for 13.56 MHz RFID Reader employing 0.18um CMOS technology, showing smaller ripple(<0.3) than that of existing systems. The designed demodulator consists of an amplifier and a detector, which consumes a power of 51.4 uWatt at 1 V biasing.

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13.56 MHz CMOS transceiver for RFID applications

Cited by 16 publications

References 7 publications

PLL-Based Contactless Energy Transfer Analog FSK Demodulator Using High-Efficiency Rectifier

PLL-Based Contactless Energy Transfer Analog FSK Demodulator Using High-Efficiency Rectifier

A complete analysis and measurement results of the threshold voltage cancellation scheme for RF to DC converter

A Low Ripple Low Power CMOS Demodulator for 13.56 MHz RFID Reader

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