14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems

Desoli, Giuseppe; Chawla, Nitin; Boesch, Thomas; Singh, Surinder-Pal; Guidetti, Elio; Ambroggi, Fabio De; Majo, Tommaso; Paolo, Zambotti; Manuj, Ayodhyawasi; Singh, Harvinder; Aggarwal, Nalin

doi:10.1109/isscc.2017.7870349

Cited by 111 publications

(70 citation statements)

References 4 publications

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“…ASICs [27], [28], [33], [ Helium, an ISA extension tailored for DSP-oriented workloads, such as an inference task. However, such an extension is not supported yet by any device.…”

Section: Performance Energy Efficiency Power Budget Flexibilitymentioning

confidence: 99%

PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors

Garofalo

Rusci

Conti

et al. 2019

Phil. Trans. R. Soc. A.

127

145

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We present PULP-NN, an optimized computing library for a parallel ultra-low-power tightly coupled cluster of RISC-V processors. The key innovation in PULP-NN is a set of kernels for quantized neural network inference, targeting byte and sub-byte data types, down to INT-1, tuned for the recent trend toward aggressive quantization in deep neural network inference. The proposed library exploits both the digital signal processing extensions available in the PULP RISC-V processors and the cluster’s parallelism, achieving up to 15.5 MACs/cycle on INT-8 and improving performance by up to 63 × with respect to a sequential implementation on a single RISC-V core implementing the baseline RV32IMC ISA. Using PULP-NN, a CIFAR-10 network on an octa-core cluster runs in 30 × and 19.6 × less clock cycles than the current state-of-the-art ARM CMSIS-NN library, running on STM32L4 and STM32H7 MCUs, respectively. The proposed library, when running on a GAP-8 processor, outperforms by 36.8 × and by 7.45 × the execution on energy efficient MCUs such as STM32L4 and high-end MCUs such as STM32H7 respectively, when operating at the maximum frequency. The energy efficiency on GAP-8 is 14.1 × higher than STM32L4 and 39.5 × higher than STM32H7, at the maximum efficiency operating point. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.

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“…ASICs [27], [28], [33], [ Helium, an ISA extension tailored for DSP-oriented workloads, such as an inference task. However, such an extension is not supported yet by any device.…”

Section: Performance Energy Efficiency Power Budget Flexibilitymentioning

confidence: 99%

PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors

Garofalo

Rusci

Conti

et al. 2019

Phil. Trans. R. Soc. A.

127

145

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show abstract

“…Given the number of designs that have been published for CNNs, we Dataset / Network Top-1 Acc. CONV / FC weights MNIST / fully connected BNN [18] 99.04 % -/ 1.19 MB SVHN / fully connected BNN [18] 97.47 % 139.7 kB / 641.3 kB CIFAR-10 / fully connected BNN [18] 89.95 % 558.4 kB / 1.13 MB ImageNet / ResNet-18 XNOR-Net [19] 51.2 % 1.31 MB / 2.99 MB ImageNet / ResNet-18 ABC-Net M=3,N=3 [21] 61.0 % 3.93 MB / 8.97 MB ImageNet / ResNet-18 ABC-Net M=5,N=5 [21] 65.0 % 6.55 MB / 14.95 MB ImageNet / ResNet-34 ABC-Net M=1,N=1 [21] 52 will focus on a more direct comparison with accelerators that explicitly target a tradeoff between accuracy and energy or performance, keeping in mind that state-of-the-art accelerators for "conventional" fixed-point accelerators such as Orlando [22] are able to reach energy efficiencies in the order of a few Top/s/W. The approaches used to reduce energy consumption in CNNs can be broadly categorized in two categories, sometimes applied simultaneously.…”

Section: Related Workmentioning

confidence: 99%

XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference

Conti¹,

Schiavone²,

Benini³

2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

110

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“…So no matter how large the decoder, there will always exist a minimum number of words above which the memory area savings are higher than the decoder overhead. In [20] 2 , the authors report an SRAM bit cell area of AB = 0.12 µm 2 in the technology we use, also for an ANN application. Given this information, we can derive rough but credible estimates of the size of a memory cut of W words of B bits each, and decide when it is interesting to use our encoding approach.…”

Section: I a R E A S Av I N G Smentioning

confidence: 99%

Efficient Decompression of Binary Encoded Balanced Ternary Sequences

Müller

Prost-Boucle

Bourge

et al. 2019

IEEE Trans. VLSI Syst.

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A balanced ternary digit, known as a trit, takes its values in {-1, 0, 1}. It can be encoded in binary as {11, 00, 01} for direct use in digital circuits. In this correspondence, we study the decompression of a sequence of bits into a sequence of binary encoded balanced ternary digits. We first show that it is useless in practice to compress sequences of more than 5 ternary values. We then provide two mappings, one to map 5 bits to 3 trits and one to map 8 bits to 5 trits. Both mappings were obtained by human analysis and lead to boolean implementations that compare quite favorably with others obtained by tweaking assignment or encoding optimization tools. However, mappings that lead to better implementations may be feasible.

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14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems

Cited by 111 publications

References 4 publications

PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors

PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors

XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference

Efficient Decompression of Binary Encoded Balanced Ternary Sequences

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