14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS

Shan, Weiwei; Yang, Minhao; Xu, Jiaming; Lu, Yue; Zhang, Shuai; Wang, Tao; Shi, Longxing; Seok, Mingoo

doi:10.1109/isscc19947.2020.9063000

Cited by 55 publications

(29 citation statements)

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“…Table 1 summarizes the comparison of our work with other recent KWS accelerators. Our design achieves 2.3–6.8X power savings compared to Shan et al (2020) among KWS accelerators. If we scale the area of our design to 28 nm it would be 0.37 mm 2 which is still slightly higher than Shan et al (2020) .…”

Section: Discussionmentioning

confidence: 97%

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Always-On Sub-Microwatt Spiking Neural Network Based on Spike-Driven Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

et al. 2021

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This paper presents a novel spiking neural network (SNN) classifier architecture for enabling always-on artificial intelligent (AI) functions, such as keyword spotting (KWS) and visual wake-up, in ultra-low-power internet-of-things (IoT) devices. Such always-on hardware tends to dominate the power efficiency of an IoT device and therefore it is paramount to minimize its power dissipation. A key observation is that the input signal to always-on hardware is typically sparse in time. This is a great opportunity that a SNN classifier can leverage because the switching activity and the power consumption of SNN hardware can scale with spike rate. To leverage this scalability, the proposed SNN classifier architecture employs event-driven architecture, especially fine-grained clock generation and gating and fine-grained power gating, to obtain very low static power dissipation. The prototype is fabricated in 65 nm CMOS and occupies an area of 1.99 mm2. At 0.52 V supply voltage, it consumes 75 nW at no input activity and less than 300 nW at 100% input activity. It still maintains competitive inference accuracy for KWS and other always-on classification workloads. The prototype achieved a power consumption reduction of over three orders of magnitude compared to the state-of-the-art for SNN hardware and of about 2.3X compared to the state-of-the-art KWS hardware.

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Section: Discussionmentioning

confidence: 97%

“…Our design achieves 2.3–6.8X power savings compared to Shan et al (2020) among KWS accelerators. If we scale the area of our design to 28 nm it would be 0.37 mm 2 which is still slightly higher than Shan et al (2020) . The higher area usage of our work is possibly because it does not adopt time-sharing in neuron hardware.…”

Section: Discussionmentioning

confidence: 97%

Always-On Sub-Microwatt Spiking Neural Network Based on Spike-Driven Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

et al. 2021

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“…However, most of the existing KWS and SV wake-up systems, limited by the high power consumption in feature extraction and recognition, can only work on the cloud [1]- [4]. MFCCs are often used in voice signal processing tasks [5]- [7], which require fast Fourier transform (FFT), discrete cosine transform (DCT), and other operations consuming lots of power despite sufficient information contained. According to the state-ofthe-art ASICs for KWS and SV, the MFCC feature extraction occupies almost 40 % (~8 μW) of the total power consumption [6].…”

Section: Introductionmentioning

confidence: 99%

“…However, massive computations and parameters are the bottlenecks of its low power implementation. Although the power consumption of [7], [8] is ultra-low, they complete VAD and KWS containing only two classes.…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Binarized Neural Network Using Analog-Intensive Feature Extraction for Keyword and Speaker Verification Wakeup

Zhao

Abubakar

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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An analog-intensive voice feature extraction method based on time-domain filtering is proposed in this paper, which solves the computational complexity problem in Mel Frequency Cepstral Coefficient (MFCC) extraction. Compared with MFCCs, the estimated power consumption of the proposed feature extraction is reduced by approximately 4×. Besides, a binarized neural network model called DSXNOR-Net with low parameters is proposed together with the generalized end-toend (GE2E) loss function for speaker verification. The feature extraction method and DSXNOR-Net are verified by Python.The proposed architecture achieves an optimal recognition accuracy of 98.3% on an English spoken digits corpus for keyword spotting (KWS) and 94.4% on TIMIT corpus for speaker verification (SV). The total estimated power consumption is reduced by approximately 2× and 4× for SV and KWS compared to the state-of-the-art results.

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“…In particular, MobileNet [14], [15] can greatly reduce the number of parameters and the computational burden by means of a separable convolution, which divides a three-dimensional (height, width, channel) filter into two simple filters, i.e., a one-dimensional (1, 1, channel) filter and a two-dimensional (height, width, 1) filter. Both MobileNet and ResNet are commonly utilized in recent analog neuron hardware [12], [16]. The classification accuracy of a recent version of MobileNet [15] (MobileNetV2) has been improved by adding a linear projection layer and through inter-channel expansion.…”

Section: Introductionmentioning

confidence: 99%

MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs

2021

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This paper proposes design strategies for a low-cost quantized neural network. To prevent the classification accuracy from being degraded by quantization, a structure-design strategy that utilizes a large number of channels rather than deep layers is proposed. In addition, a squeeze-and-excitation (SE) layer is adopted to enhance the performance of the quantized network. Through a quantitative analysis and simulations of the quantized key convolution layers of ResNet and MobileNets, a low-cost layer-design strategy for use when building a neural network is proposed. With this strategy, a low-cost network referred to as a MixedNet is constructed. A 4-bit quantized MixedNet example achieves an on-chip memory size reduction of 60% and fewer memory access by 53% with negligible classification accuracy degradation in comparison with conventional networks while also showing classification accuracy rates of approximately 73% for Cifar-100 and 93% for Cifar-10.INDEX TERMS Convolutional neural network, deep neural network, memory access number, memory cost, on-chip memory size, quantized neural networks.

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14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS

Cited by 55 publications

References 1 publication

Always-On Sub-Microwatt Spiking Neural Network Based on Spike-Driven Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

Always-On Sub-Microwatt Spiking Neural Network Based on Spike-Driven Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

An Energy-Efficient Binarized Neural Network Using Analog-Intensive Feature Extraction for Keyword and Speaker Verification Wakeup

MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs

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