14‐3: Extremely Short‐Channel LTPS TFT Technologies for High‐Performance Low‐Power, and Reliable AMOLED displays

Abstract

This paper presents recent progress to scale down low‐temperature polysilicon (LTPS) TFT technologies in the extremely short‐channel length regime for AMOLED displays. Process integration of short‐channel gate and narrow‐width polysilicon into scaled equivalent gate‐oxide thickness (EOT), is explored, in conjunction with enhanced poly crystallization by reducing defect density‐of‐state (DOS) especially in the grain boundaries of the channel region. We obtain more than twice higher current drive (Ion) with significantly‐reduced parasitic gate capacitance, thereby enabling high‐performance high‐frequency panel operations. In addition to superior panel performance in scaled LTPS TFTs, reliable devices are attained, demonstrating robust device characteristics for negative‐bias instability (NBTI) and hot carrier injection (HCI) effects. Physics‐based analysis, based on experimental data and numerical device simulations, is performed to gain more insight in the TFT technologies.

Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

“…4,5 This fundamental benefit can be applied to lowtemperature polysilicon (LTPS) thin-film transistor (TFT) structures in display applications using optimal bottom gate-controlled device structures. 6 As recently reported, bottom gate-aided LTPS TFTs can potentially offer better image quality and recoverable residual image sticking, especially in flexible displays due to shielding the electric fields from polyimide charging effects. 7,8 Furthermore, high-performance LTPS TFTs can potentially offer high image quality and low recoverable residual images, particularly in high-frequency operations because of high Ion and low (parasitic) Cgs.…”

“…Finally, it is noticed that, in the extremely scaled pixels, stacked device structures can be more applicable 6 . In such BP architecture, bottom gate‐controlled LTPS TFTs are more favorable due to shielding effects from the lower device.…”

“…Finally, it is noticed that, in the extremely scaled pixels, stacked device structures can be more applicable. 6 In such BP architecture, bottom gate-controlled LTPS TFTs are more favorable due to shielding effects from the lower device. Figure 7A,B shows schematics of stacked LTPS TFT structures without a bottom gate for the upper LTPS TFT and with a bottom gate for upper LTPS TFT, respectively.…”

“…In first‐principle physics, the double‐gate field‐effect transistors appear more electrostatic than the single‐gate counterparts due to the electrical coupling of two gates 4,5 . This fundamental benefit can be applied to low‐temperature polysilicon (LTPS) thin‐film transistor (TFT) structures in display applications using optimal bottom gate‐controlled device structures 6 . As recently reported, bottom gate‐aided LTPS TFTs can potentially offer better image quality and recoverable residual image sticking, especially in flexible displays due to shielding the electric fields from polyimide charging effects 7,8 .…”

“…7,8 Furthermore, high-performance LTPS TFTs can potentially offer high image quality and low recoverable residual images, particularly in high-frequency operations because of high Ion and low (parasitic) Cgs. 9,10 In high-frequency and variable refresh rate (VRR) operations, 11 high Ion and low (parasitic) Cgs will more significantly impact on display performance. 12 For fast refresh rate and/or high-resolution panels, the scan-on-time is reduced to be shorter (e.g., ≤2.0 μs), and thus faster charging process to the storage capacitance (CST) through TFTs is required.…”