14nm FinFET process technology platform for over 100M pixel density and ultra low power 3D Stack CMOS Image Sensor

Yu, Donghee; Choi, Jong-Won; Jung, Sungmoon; Kwon, Minho; Ha, Il-Seon; Kim, Chae-Sung; Cho, Sang Hyun; Lim, Sanghyeok; Kim, Won-Woong; Kim, Moo-Young; Park, Seonghye; Lee, Choong Jae; Lee, Ki‐Don; Ranjan, Rakesh; Maeda, S.; Jeong, Gitae; Park, Myounkyu; Park, Jung Hwan; Hwang, Seongtaek; Lee, Joonhyung; Yu, Sung-Hun; Shin, Hyunjung; Kim, ByoungHo

doi:10.1109/iedm19573.2019.8993567

Cited by 5 publications

(2 citation statements)

References 2 publications

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“…This is because the semiconductor fabrication technology, quantified by the process node, of the sensor usually lags at least one generation behind that of the processor. Today, many commercial processors are fabricated using a 7 nm process node or smaller, but even high-end image sensors still use a 14 nm or 28 nm process node [58,87]. The computation power consumption increases quadratically with respect to the process node [25].…”

Section: Reducing Sensor Data Transmissionmentioning

confidence: 99%

Real-Time Gaze Tracking with Event-Driven Eye Segmentation

Ye¹,

Goulding-Hotta²,

Khan³

et al. 2022

Preprint

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Workflow of our gaze tracking algorithm. The algorithm provides an Auto ROI mode (akin to the conventional "3A" algorithms in a camera) by emulating an event camera in software and using the events to predict the Region of Interest (ROI). Performing Auto ROI in emerging compute-capable image sensors further reduces the data transmission energy. Right: Our algorithm achieves sub-0.5°gaze accuracies (both horizontal and vertical directions) using only 30K parameters, an order of magnitude smaller than other algorithms. Marker sizes in the figure are proportional to the number of parameters. The algorithm operates at over 30 Hz on a mobile Jetson Xavier processor.

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Section: Reducing Sensor Data Transmissionmentioning

confidence: 99%

Real-Time Gaze Tracking with Event-Driven Eye Segmentation

Ye¹,

Goulding-Hotta²,

Khan³

et al. 2022

Preprint

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show abstract

“…Samsung has moved toward 0.7 lm pixel on 65 nm technology with logic and signal processor on 14 nm FinFET technology recently. The 144 MP BSI-CIS using 14 nm technology for logic chip gains 42% power consumption reduction over logic chip processed by 28 nm [10]. A 12 MP dual photodiode (2PD) BSI-CIS is explored in the 65 nm-14 nm processing technology and gains 29% power consumption reduction over that processed by 65 nm-28 nm technologies.…”

Section: The Stacked Rgb Backside Illuminated-cmos Imagementioning

confidence: 99%

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Lu¹

2021

Journal of Electronic Packaging

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Numerous technology breakthroughs have been made in image sensor development in the past two decades. Image sensors have evolved into a technology platform to support many applications. Their successful implementation in mobile devices has accelerated market demand and established a business platform to propel continuous innovation and performance improvement extending to surveillance, medical, and automotive industries. This overview briefs the general camera module and the crucial technology elements of chip stacking architectures and advanced interconnect technologies. This study will also examine the role of pixel electronics in determining the chip stacking architecture and interconnect technology of choice. It is conducted by examining a few examples of CMOS Image Sensors (CIS) for different functions such as visible light detection, Single Photon Avalanche Photodiode (SPAD) for low light detection, rolling shutter and global shutter, and depth sensing and Light Detection And Ranging (LiDAR). Performance attributes of different architectures of chip stacking are overviewed. Direct bonding followed by Via-last through silicon via (Via-last TSV) and hybrid bonding (HB) technologies are identified as newer and favorable chip-to-chip interconnect technologies for image sensor chip stacking. The state-of-the-art ultra-high-density interconnect manufacturability is also highlighted.

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Self-heating effect of GAAFET and FinFET for over 2-V applications using TCAD simulation

Hwang

Yun

2022

2022 International Conference on Electronics, Information, and Communication (ICEIC)

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14nm FinFET process technology platform for over 100M pixel density and ultra low power 3D Stack CMOS Image Sensor

Cited by 5 publications

References 2 publications

Real-Time Gaze Tracking with Event-Driven Eye Segmentation

Real-Time Gaze Tracking with Event-Driven Eye Segmentation

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Self-heating effect of GAAFET and FinFET for over 2-V applications using TCAD simulation

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