15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization

Guo, Ruiqi; Yue, Zhiheng; Si, Xin; Hu, Te; Li, Hao; Tang, Limei; Wang, Yabing; Liu, Leibo; Chang, Meng‐Fan; Li, Qiang; Wei, Shaojun; Yin, Shouyi

doi:10.1109/isscc42613.2021.9365989

Cited by 28 publications

(6 citation statements)

References 4 publications

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“…CMOS ANN hardware for inference has already achieved high energy efficiency of more than 600 TOPS/W with MAC operations based on a CIM architecture [29] by limiting the bit-width of the synaptic weights as shown in Table 4. The energy efficiency is higher than that of ANN hardware using ReRAM [10], [28].…”

Section: Discussionmentioning

confidence: 99%

A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain

Uenohara

Aihara

2022

IEEE Access

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We present a mixed-signal spiking neural networks processor with 8-bit synaptic weight onchip learning in 40 nm CMOS that consists of a 10k mixed-signal synapse circuit and 100 analog leaky integrate-and-fire (LIF) neuron circuits. The processor has no clock signal except in peripheral circuits for I/O, and neuron and synapse circuits can operate asynchronously in the continuous-time domain, just like biological neurons. We demonstrate the energy efficiency of 6.24-18.7 TOPS/W in a multitarget spike learning task.INDEX TERMS ReSuMe, on-chip learning, compute-in-memory, CIM, spiking neural networks, SNN

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Section: Discussionmentioning

confidence: 99%

A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain

Uenohara

Aihara

2022

IEEE Access

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“…If a deep learning accelerator runs a big model with limited on-chip memory resources, TTD is a good choice to help it avoid a large size of memory footprint. However, it may be necessary to design a domain-specific accelerator for handling the increased computation cost and improving energy efficiency, by taking advantage of reduced external memory accesses, such as [38], [39].…”

Section: Train-ttd-trainmentioning

confidence: 99%

TT-MLP: Tensor Train Decomposition on Deep MLPs

Yan

Ando

et al. 2023

IEEE Access

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Deep multilayer perceptrons (MLPs) have achieved promising performance on computer vision tasks. Deep MLPs consist solely of fully-connected layers as the conventional MLPs do but adopt more sophisticated network architectures based on mixer layers composed of token-mixing and channelmixing components. These architectures enable deep MLPs to have global receptive fields, but the significant increase of parameters becomes a massive burden on practical applications. To tackle this problem, we focus on using tensor-train decomposition (TTD) for compressing deep MLPs. At first, this paper analyzes deep MLPs under conventional TTD methods, especially using various designs of a macro framework and micro blocks: The former is how to concatenate mixer layers, and the latter is how to design a mixer layer. Based on the analysis, we propose a novel TTD method named Train-TTD-Train. The proposed method exerts the learning capability of channel-mixing components and improves the trade-off between accuracy and size. In the evaluation, the proposed method showed a better trade-off than conventional TTD methods on ImageNet-1K and achieved a 0.56% higher inference accuracy with a 15.44% memory reduction on Cifar-10.INDEX TERMS Tensor-train decomposition, low-rank approximation, deep neural networks, deep multilayer perceptron, network parameter compression.

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“…To utilize both digital and CIM architecture for optimal performance on the various layer characteristics, a low-power SoC, comprising a digital neural network accelerator, an analog CIM core and a RISC-V CPU, is designed to realize simultaneous execution of subsequent layers and high/low precision on corresponding cores [25] . Algorithm-hardware co-design method is utilized for higher energy efficiency.…”

Section: System-level Cim Chipsmentioning

confidence: 99%

Trending IC design directions in 2022

Chan¹,

Cheng²,

Deng³

et al. 2022

J. Semicond.

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For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

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15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization

Cited by 28 publications

References 4 publications

A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain

A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain

TT-MLP: Tensor Train Decomposition on Deep MLPs

Trending IC design directions in 2022

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