15-nm-thick Si channel wall vertical double-gate MOSFET

Masahara, Meishoku; Matsukawa, Takashi; Ishii, Keisuke; Liu, Yongxun; Tanoue, H.; Sakamoto, K.; Sekigawa, Toshihiro; Yamauchi, H.; Kanemaru, S.; Suzuki, Eiichi

doi:10.1109/iedm.2002.1175994

Cited by 19 publications

(18 citation statements)

References 2 publications

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“…The gate electrode was polysilicon and polysilicon depletion was taken into account. It can be seen that satisfactory agreement between simulated and experimental characteristics is obtained when the surface roughness factor in the CVT model is reduced from (elec) = 5.82×10 14 and (holes) = 2.0546×10 14 to (elec) = 2.91×10 13 and (holes) = 1.027×10 13 .…”

Section: Modeling Proceduresmentioning

confidence: 78%

“…Therefore, fully depleted double (DG) or surround gate MOSFETs are extremely promising for high density, low voltage, and low power DRAM, SRAM, and conventional CMOS applications. Technologically these fully depleted double or surround gate MOSFETs can be realized using DG SOI [2,3,[6][7][8], FinFETs [9][10][11] or vertical MOSFETs [12][13][14][15][16][17]. Though a major advantage of DG SOI and FinFET technologies is the ease of device isolation, in most cases the body is left floating and hence, these devices can suffer from floating body effects whereby weak avalanche in the drain causes hole injection to the body which raises the potential there.…”

Section: Introductionmentioning

confidence: 99%

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Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

et al. 2016

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Abstract:Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate-gate charge coupling are investigated at pillar thicknesses in the range 200-10 nm. For pillar thickness > 120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses < 60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60-120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behaviour are characterized as a function of pillar thickness and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate-gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation., whereas for pillar thicknesses < 60 nm, the increase in the drain current is found to be governed by the inherent gate-gate charge coupling. Abstract Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate-gate charge coupling are investigated at pillar thicknesses in the range 200-10 nm. For pillar thickness > 120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses < 60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60-120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behaviour are characterized as a function of pillar thickness and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate-gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the...

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Section: Modeling Proceduresmentioning

confidence: 78%

Section: Introductionmentioning

confidence: 99%

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

et al. 2016

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“…The top gate is typically used to switch the transistor ON and OFF, while the bottom gate is used for dynamic (or static) V th adjustment. In the vertical conduction structures [89,90], the current flows between the source and drain in the vertical direction along two or more vertical channel surfaces. The main advantage of this structure is that the channel length is defined by epitaxy rather than by lithography.…”

Section: Double-gate Mosfetmentioning

confidence: 99%

“…The transistors that use independently controlled gates are not limited to only two gates, but for the geometrical reasons of the transistor and the connectivity of the transistor terminals, it is suitable to use only two gates. The independent doublegate transistors can be used to implement the universal logic functionality within a single transistor [90]. Gidon [91] has investigated the two-dimensional DG MOSFET and combated the high aspect ratio of the transistor (thin channel compared to its length) by introducing an anisotropy scale factor in its geometry.…”

Section: Double-gate Mosfetmentioning

confidence: 99%

Introduction

Srivastava

Singh

2013

Analog Circuits and Signal Processing

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“…The fabrication process of planar DG MOSFETs is relatively complicated and the device is difficult to achieve the self-alignment of top and bottom gates. Vertical channel double gate MOSFET is another kind of DG device with easily self-aligned double gates and the channel length not defined by lithography technology [112,113] . However, the device may exhibit high parasitic resistance.…”

Section: Non-classical Device Architecturesmentioning

confidence: 99%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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15-nm-thick Si channel wall vertical double-gate MOSFET

Cited by 19 publications

References 2 publications

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Introduction

Challenges of 22 nm and beyond CMOS technology

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