16.9 4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur

Kennedy, Michael Peter; Donnelly, Yann; Breslin, J. T.; Tulisi, Stefano; Patil, Sanganagouda; Curtin, Ciaran; Brookes, Stephen; Shelly, Brian; Griffin, Patrick; Keaveney, Mike

doi:10.1109/isscc.2019.8662327

Cited by 12 publications

(9 citation statements)

References 4 publications

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“…Next, θ DLF is calculated according to (9), where the required parameters can be obtained from the PLL settings-ρ/α from the configurations of the DLF, and FCW frac,s from the FCW to be used for the A SC optimization in the next step [see Fig. 11(b)].…”

Section: B Procedures To Determine the Spur Cancellation Patternmentioning

confidence: 99%

Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop

Gao,

Bogdan Staszewski,

Babaie

2024

IEEE J. Solid-State Circuits

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Parasitic coupling between the building blocks within a fractional-N phase-locked loop (PLL) can result in noticeable spurs in its output spectrum, thus affecting the PLL's usability in ultralow jitter applications. In this article, we focus on a chief contributor-"self-interference" caused by coupling from the PLL's frequency-reference (FREF) clock buffer to the RF oscillator, while exploiting the fact that the resulting phasedisturbance pattern: 1) exhibits a sinusoidal shape and 2) is synchronized with the PLL's output clock phase. Accordingly, we propose a digitally intensive pattern-aware approach to suppress the fundamental fractional spur raised by this selfinterference mechanism. The proposed technique is applied to a fabricated digital PLL chip and reduces the worst spur level by 13 dB, thus proving its effectiveness.

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Section: B Procedures To Determine the Spur Cancellation Patternmentioning

confidence: 99%

Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop

Gao,

Bogdan Staszewski,

Babaie

2024

IEEE J. Solid-State Circuits

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“…The synthesizer is based on an identical architecture to that described in [17] and [18] and has a similar power consumption. It comprises a type-II CP fractional-N frequency synthesizer implemented in a 180-nm SiGe BiCMOS process [17]. A bipolar CP operating from a 5-V supply is employed.…”

Section: A Synthesizermentioning

confidence: 99%

Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer

Mai

Donnelly²,

Kennedy

et al. 2022

IEEE J. Solid-State Circuits

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Fractional-N frequency synthesizers that use a digital -modulator (DDSM) to control the feedback divider can exhibit spurious tones that move about in the frequency domain; these are known colloquially as "walking" or wandering spurs. Building upon a theoretical explanation of the origin of wandering spurs, this article presents two methods to suppress them. It describes a 4.9-GHz 180-nm SiGe BiCMOS charge-pump phase-locked loop (CP-PLL) fractional-N frequency synthesizer platform with a divider controller that can function as: 1) a standard MASH 1-1-1; 2) a MASH 1-1-1 with high-amplitude dither; and 3) a MASH 1-1-1 with a modified third stage. Measurements confirm the effectiveness of the wandering spur suppression strategies.

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“…The MASH-SR is a hybrid between these two classes of divider controllers. It has a nested-cascaded structure that consists of a MASH DDSM and cascaded quantization blocks [14], [15], [16], [17]. The input to the divider controller is partitioned and quantized by a MASH and a SR. Consequently, fewer quantization blocks are needed to perform the quantization of the divider controller input.…”

mentioning

confidence: 99%

Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers

Mai

Kennedy

2023

IEEE Trans. Circuits Syst. I

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The divider controller in a conventional phase-locked loop fractional-N frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.

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16.9 4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur

Cited by 12 publications

References 4 publications

Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop

Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop

Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer

Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers

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