ESSDERC 2008 - 38th European Solid-State Device Research Conference 2008
DOI: 10.1109/essderc.2008.4681711
|View full text |Cite
|
Sign up to set email alerts
|

16-Gigabit, 8-level NAND flash memory with 51nm 44-cell string technology

Abstract: Eight-level NAND flash memories with 51nm design rule and 44-cell string floating gate technology have been successfully developed for the first time. 44-cell string with floating poly silicon and tungsten silicide (WSi) gate structure reduced the cell area per bit and improved chip cost efficiency. 44-cell string structure shows acceptable cell current and the results of endurance and interference are quite comparable to the conventional 32-cell string structure.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Publication Types

Select...

Relationship

0
0

Authors

Journals

citations
Cited by 0 publications
references
References 9 publications
0
0
0
Order By: Relevance

No citations

Set email alert for when this publication receives citations?