16 x 16 VCSEL array flip-chip bonded to CMOS VLSI circuit

Krishnamoorthy, Ashok V.; Goossen, K.W.; Chirovsky, L. M. F.; Rozier, R. Gary; Chandramani, P.; Hui, S.P.; Lopata, J.; Walker, J.; D'Asaro, L.A.

doi:10.1109/68.868012

Cited by 56 publications

(23 citation statements)

References 5 publications

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“…Optical interconnects based on complimentary-metal-oxidesemiconductor CMOS/VCSEL technologies have been widely proposed for high-performance computing applications [16], [17]. The approach followed in our design is the most widely used hybrid integration using flip-chip bonding of OE-VLSI components.…”

Section: B Optical Integration Methodologymentioning

confidence: 99%

“…Note, that the total remote losses are added to the total local losses to give 10.1 dB 0.225 dB 3 dB . Now, with , the number of groups that can be connected is approximately 16. This implies that RAPID can scale up to nodes, though current board sizes limit the number of nodes per board to 4, and the system size to 16 nodes.…”

Section: B Power Budget and Ber Estimationmentioning

confidence: 99%

“…GaAs substrate can then be selectively etched leaving the VCSEL/PD contact pad on the backside of the wafer and all optical sources/detectors on the other side of the wafer. The VCSELs and PDs can now be integrated onto the CMOS driver using flip-chip bonding and substrate removal techniques [11], [16].…”

Section: B Optical Integration Methodologymentioning

confidence: 99%

“…Recently, there have been significant developments in optical and optoelectronic devices (vertical cavity surface emitting laser and photodetector arrays [10]- [12], arrayed waveguide grating [13], [14], microoptical components [15], etc.) and packaging technologies (OE-VLSI heterogeneous integration [16], smart pixel technology [17]) which make optical interconnects a viable and cost-effective option for building high bandwidth, low latency, and scalable optical interconnection networks.…”

Section: A Optical Interconnects For Distributed Shared Memory Multimentioning

confidence: 99%

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RAPID: Reconfigurable and Scalable All-Photonic Interconnect for Distributed Shared Memory Multiprocessors

Kodi

Louri

2004

J. Lightwave Technol.

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Abstract-In this paper, we describe the design and analysis of a scalable architecture suitable for large-scale distributed shared memory (DSM) systems. The approach is based on an interconnect technology which combines optical components and a novel architecture design. In DSM systems, numerous shared memory transactions such as requests, responses and acknowledgment messages propagate simultaneously in the network. As the network size increases, network contention results in increasing the critical remote memory access latency, which significantly penalizes the performance of DSM systems. In our proposed architecture called reconfigurable and scalable all-photonic interconnect for distributed-shared memory (RAPID), we provide high connectivity by maximizing the channel availability for remote communication to reduce the critical remote latency. RAPID provides fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed wavelength division multiplexing (WDM), time division multiplexing (TDM), and space division multiplexing (SDM) techniques. RAPID is wavelength-routed, permitting the same limited set of wavelength to be reused among all processors. We evaluated RAPID based on network characteristics, power budget criteria, and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh, and hypercube networks. We found that RAPID outperforms all networks and still provides good performance as the network is scaled to very large numbers.Index Terms-Cache coherence, distributed shared memory, optical interconnects, scalable optical networks.

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Section: B Optical Integration Methodologymentioning

confidence: 99%

Section: B Power Budget and Ber Estimationmentioning

confidence: 99%

Section: B Optical Integration Methodologymentioning

confidence: 99%

Section: A Optical Interconnects For Distributed Shared Memory Multimentioning

confidence: 99%

See 2 more Smart Citations

RAPID: Reconfigurable and Scalable All-Photonic Interconnect for Distributed Shared Memory Multiprocessors

Kodi

Louri

2004

J. Lightwave Technol.

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“…Currently, hybrid integration, based on flip-chip bonding, is the most mature technology for the combination of III-V optoelectronics with Si ICs [1]- [2]. The main drawback of the hybrid approach is the demanding fabrication sequence which results in increased manufacturing cost.…”

Section: Hybrid Integration-technologiesmentioning

confidence: 99%

High density Integrated Optoelectronic Circuits for High Speed Photonic Microsystems

Minoglou

Kyriakis-Bitzaros

Katsafouros

et al. 2007

2007 Ph.D Research in Microelectronics and Electronics Conference

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Abstract. The study of high density integrated optoelectronic circuits involves the development of hybrid integration technologies and the generation of models for the optoelectronic devices. To meet these goals, in the beginning a methodology for the heterogeneous integration of epitaxial GaAs wafers with fully processed standard bipolar complementary metal-oxide-semiconductor Si wafers is presented. The complete low-temperature wafer bonding process flow, based on SOG/SIO 2 , including procedures for the Si wafer planarization and GaAs substrate removal, has been developed and evaluated. The implementation of an in-plane optical link, consisting of an edge-emitting laser diode, a waveguide and a photodiode, is demonstrated. Further investigation on heterogeneous integration is achieved by presenting a second methodology. The integration of complete optoelectronic dies, consisting of optical sources and detectors connected by waveguides for the employment of a photonic layer above CMOS integrated circuits has been proposed. Photonic dies are integrated to CMOS circuits through a novel metallic bonding technique that utilizes a thin multilayer structure of the Au-20Sn eutectic alloy along with a starting layer of a rare earth element (Gd). Its main advantage is the accomplishment of mechanical bonding and electrical connectivity of the heterogeneous devices in a single step. The study of photonic microsystems demands also the modeling of specific OE devices. Under this scope, an efficient model scheme that combines the non-linear behavior of the input parasitics with the intrinsic fundamental device rate equations of the Vertical Cavity Surface Emitting Lasers (VCSELs) is proposed. A systematic methodology for the model parameter extraction from dc and ac, electrical and optical measurements, is also presented and simulation results are compared with the experimental measurements. Extraction and simulation procedures are implemented in commercial integrated circuit design tools and they are proved to be very fast while they preserve adequate accuracy.

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Regional Pulsewidth and Delay Nonuniformity of Modulated 940 nm Vertical‐Cavity Surface‐Emitting Laser Array

Cheng

et al. 2022

Advanced Photonics Research

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Under pulsed modulation, the emission uniformity in terms of pulsewidth and delay of a 940 nm multimode vertical‐cavity surface‐emitting laser (MM‐VCSEL) array is characterized by analyzing the position‐dependent pulsating and chirping dynamics among localized 600 VCSEL elements. In addition, the MM‐VCSEL array biased nearly threshold current (Ith) of 350 mA with a low resistance of 0.72 Ω reveals serious impedance mismatching with a high reflection coefficient (Γ) of −0.97. The MM‐VCSEL array biased below threshold (at Idc: ≈0.9 Ith) reveals low‐impedance and high‐capacitance behavior to result in large modulation reflection with allowable −3 dB bandwidth of 0.8 GHz. The nonuniform optical intensity and delay distribution among all MM‐VCSEL elements corroborate that the gradually enlarged inductance attenuates the modulation current away from bond wires. By modulating the 0.9Ith‐biased MM‐VCSEL array with an 127 ps‐wide electrical pulse with a peak amplitude of 15.3 V, a multimode fiber probe collects the single MM‐VCSEL output with average power, peak voltage, and pulsewidth of 0.08 mW, 25.1 mV, and 602 ps. The delay time as large as 273.4 ps between the nearest and farthest parts of local MM‐VCSEL elements in the array determines its impulse response and uniformity for applications.

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16 x 16 VCSEL array flip-chip bonded to CMOS VLSI circuit

Cited by 56 publications

References 5 publications

RAPID: Reconfigurable and Scalable All-Photonic Interconnect for Distributed Shared Memory Multiprocessors

RAPID: Reconfigurable and Scalable All-Photonic Interconnect for Distributed Shared Memory Multiprocessors

High density Integrated Optoelectronic Circuits for High Speed Photonic Microsystems

Regional Pulsewidth and Delay Nonuniformity of Modulated 940 nm Vertical‐Cavity Surface‐Emitting Laser Array

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