17.2: A Novel Five‐PhotoMask LTPS CMOS Structure with Improved Storage Capacitor for AMLCD Application

Abstract

A novel five-mask low temperature polycrystalline silicon (LTPS) complementary metal oxide semiconductor (CMOS) structure was verified by manufacturing the thin film transistor (TFT) test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective storage area formation process was developed, without additional photo mask steps, to solve the sputtering damage encountered inevitably in the contact between polycrystalline silicon (p-Si) and storage metal. In addition, the selectively thin dielectric layer increased capacitance per unit area, and thus, increased the aperture ratio of AMLCD panel by reducing the capacitor area without reducing GI thickness in TFT