180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

Abstract

A wide range delay-locked loop (DLL) based clock and data recovery (CDR) circuit including coarse and fine tune blocks is proposed in this paper. The coarse tune block adopts a time to digital converter and digital control delay line to widen the frequency capture range, reduce locking time and prevent the false locking problem. In the fine tune block, a novel phase detector combines the tasks of sampling and charge-pump using half rate clock. Starting-control circuit can ensure CDR takes full use of the delay range provided by voltage control delay line. Moreover, a fully analog DLL technique is applied to exploit the benefits of low skew and jitter performance. The simulation result shows the proposed CDR can cover a wide frequency range from 180.5Mbps to 8Gbps, while the peak-to-peak jitter of recovery clock is 2.7ps at 200Mbps and 1.06ps at 8Gbps. Fabricated in a 65nm CMOS process, this design dissipates 9.9mW and 22.9mW respectively at 200 Mbps and 8Gbps from a 1.2 V supply. Keywords-Clock and data recovery (CDR), wide-range, delaylocked loop (DLL), low jitter, time-to-digital converter (TDC)

Delay‐locked loop based clock and data recovery with wide operating range and low jitter in a 65‐nm CMOS process

“…As shown in Figure (a), the DCDL acts as a coarse delay line which is similar to our previous work in . This structure enables a wide adjustable range without increasing the intrinsic delay.…”

“…The time‐to‐digital converter (TDC) structure in our previous work can finish the coarse tuning lock in one clock cycle. However, the mismatch between the TDC and DCDL's delay time resulting from process variation, the phase jitter of clk and data because of power supply voltage and temperature change, may lead to a false lock.…”

“…Unlike realization of the analog circuit , this FPD is implemented using digital logic, which can easily migrate to any process technology, achieve robust operation and reduce hardware cost. The fine delay unit (FDU) used in the VCDL can realize fine precision, and the cross‐coupled inverters can suppress skew between the complementary signals to ensure a good duty ratio. Meanwhile, to finish fine locking, the delay range of VCDL, T fine_range , in the FTB should be larger than T PG2 .…”

A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

“…The first structures are using feedback phase tracking like Phase Locked Loop (PLL) or Delay Locked Loop (DLL). These closed-loop architectures are the most used essentially for their low jitter [1,2,5,6]. The second ones are open loop structures with low power, fast locking time, and simple and low-cost design [7].…”

“…In the field of CDR architectures, closed-loop systems, such as Phase Locked Loop (PLL) and Delay Locked Loop (DLL), excel in providing low-jitter performance, making them the preferred choice in many applications [1][2][3][4][5][6]. However, open-loop CDR structures offer distinct advantages, particularly in terms of low power consumption, fast locking time, and simplicity of design, often resulting in cost-effective solutions [7].…”