19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fs&lt;inf&gt;rms&lt;/inf&gt; jitter

Hussein, Ahmed I.; Vasadi, Sriharsha; Soliman, Mazen; Paramesh, Jeyanandh

doi:10.1109/isscc.2017.7870393

Cited by 8 publications

(5 citation statements)

References 3 publications

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“…In [6], a 60 GHz chipset with 22.5-26.23 GHz integrated PLL, which achieved a phase noise of −92 dBc/Hz at 1 MHz offset, was realized with 0.13 μm BiCMOS process. In [7,8], all-digital mmWave PLL (ADPLL) was realized, but its in-band phase noise performance was limited to around −85 dBc/Hz. To improve the phase noise performance and attenuate the parasitic effect on the circuit operating frequency, frequency multiplication techniques, such as the injection locked oscillator [9,10], harmonic extraction [11],…”

Section: Introductionmentioning

confidence: 99%

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

Niu

et al. 2022

Electronics

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This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

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Section: Introductionmentioning

confidence: 99%

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

Niu

et al. 2022

Electronics

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“…To improve the performance of a PLL, many aspects can be considered including the utilisation of digital controlled oscillator instead of VCO [9,[12][13][14], counter and comparator based logic [15] or implementing reference injected structure [16], etc. Among the basic building blocks of a PLL, the PFD is one of the important parts and its interaction with CP affects widely the general performance of the PLL.…”

Section: Introductionmentioning

confidence: 99%

Fast‐locking PLL based on a novel PFD‐CP structure and reconfigurable loop filter

Abolhasani

Mousazadeh

Khoei

2020

IET Circuits, Devices & Systems

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“…Equation (41), (30), (32), (36), (39), and (40) predicts that over the subset of [6 GHz,7 GHz] the frequency of the DCO will be: 29. Using excel, the trend line and coefficient of correlation is also given on the plot.…”

Section: Example Of Using R 2 Field Mapsmentioning

confidence: 99%

“…If two current mirrors are used to sink or source the oscillator (one at each source node of each negative gm transistor), then banks (like those in Figure 32) can also be implemented on the source side of the negative gm transistors. The resulting effect would be that the capacitance of the banks on the source side would translate to the drain side of the transistors (and hence adding capacitance to the overall tank capacitance) by a factor given by [36] - [39]:…”

Section: Banks On Source Side Of Negative Gm Transistorsmentioning

confidence: 99%

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Design of a Linear LC Digitally Controlled Oscillator Using Topographical Field Maps

Abdullah¹

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19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fs<inf>rms</inf> jitter

Cited by 8 publications

References 3 publications

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

Fast‐locking PLL based on a novel PFD‐CP structure and reconfigurable loop filter

Design of a Linear LC Digitally Controlled Oscillator Using Topographical Field Maps

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