19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming

Park, Ki-Tae; Han, Jin-Man; Kim, Daehan; Nam, Sang-Wan; Choi, Kihwan; Kim, Minsu; Kwak, Pansuk; Lee, Doo-Sub; Choi, Yong‐Sang; Kang, Kyung-Min; Choi, Minsuk; Kwak, Donghun; Park, Hyun-wook; Shim, Sang-Won; Yoon, Hyun-Jun; Kim, Doo-Hyun; Park, Sang-won; Lee, Kangbin; Ko, Kuihan; Shim, Dong-Kyo; Ahn, Y. H.; Park, Jeunghwan; Ryu, Jiseon; Kim, Dong-Hyun; Yun, Kyungwa; Kwon, Joonsoo; Shin, Sanghoon; Youn, Dongkyu; Kim, Won‐Tae; Kim, Tae Hyun; Kim, Sungjun; Seo, Sungwhan; Kim, Hyung-Gon; Byeon, Dae–Seok; Yang, Hyang-Ja; Kim, Moosung; Kim, Myong-Seok; Yeon, Jinseon; Jang, Jae Hoon; Kim, Han‐Soo; Lee, Woonkyung; Song, Duheon; Lee, Sungsoo; Kyung, Kye-Hyun; Choi, Jung Kyu

doi:10.1109/isscc.2014.6757458

Cited by 86 publications

(27 citation statements)

References 3 publications

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“…A V-NAND structure is also a GAA vertical-type cell [17,18]. It is derived from the original TCAT architecture [19].…”

Section: The V-nand Architecturementioning

confidence: 99%

“…It must be noted here that the overall performance of the 3D NAND architectures should be finally evaluated after a proper system implementation. In fact, several drawbacks of an architecture can be corrected or mitigated by implementing ad hoc program algorithms and ECC [4,17,31,32,[34][35][36][37].…”

Section: Comparison Between Ct Flat Cell and Gaa Cell Structuresmentioning

confidence: 99%

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3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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Abstract:In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.

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“…A V-NAND structure is also a GAA vertical-type cell [17,18]. It is derived from the original TCAT architecture [19].…”

Section: The V-nand Architecturementioning

confidence: 99%

Section: Comparison Between Ct Flat Cell and Gaa Cell Structuresmentioning

confidence: 99%

3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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“…In this field, a pioneering proposal was put forward in 2001 [16], evolving into early proposals based on layer stacking [17][18][19] and reaching the first cost-effective solution of a 3D-integrated array in 2007 [20]. From there on, 3D NAND based on vertical channels have taken the lead in the quest for higher density, resulting in the first commercial product in 2013 [21,22] and reaching a capacity of 786 Gb with a density of 4.29 Gb/mm 2 [23] while stacking up to 64 layers [23][24][25]. Chip capacity was boosted not only by 3D integration, but also by multi-bit storage: while two bit-per-cell (i.e., multi-level cells, MLCs) were used in the first prototype [21], today's technology relies on storing three bit-per-cell (triple-level cells or TLCs) and quadruple-level cells (QLCs) are under active development.…”

Section: Introductionmentioning

confidence: 99%

“…From there on, 3D NAND based on vertical channels have taken the lead in the quest for higher density, resulting in the first commercial product in 2013 [21,22] and reaching a capacity of 786 Gb with a density of 4.29 Gb/mm 2 [23] while stacking up to 64 layers [23][24][25]. Chip capacity was boosted not only by 3D integration, but also by multi-bit storage: while two bit-per-cell (i.e., multi-level cells, MLCs) were used in the first prototype [21], today's technology relies on storing three bit-per-cell (triple-level cells or TLCs) and quadruple-level cells (QLCs) are under active development. Recent reviews of the different 3D NAND technologies and architectures can be found in [26][27][28].…”

Section: Introductionmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…Since 3D NAND Flash has come to market in 2014 [1], the memory array size has been nearly doubled every year [2,3,4]. The increasing density of 3D NAND flash array causes the increasing parasitic capacitance of word lines (WLs).…”

Section: Introductionmentioning

confidence: 99%

A 1.2 mV ripple, 4.5 V charge pump using controllable pumping current technology

Huang

Wang

Chen

et al. 2017

IEICE Electron. Express

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This paper represents a 4.5 V regulated charge pump with extremely small ripple. The pump designed with Voltage Doubler (VD) significantly reduces the output ripple voltage. In addition, this circuit utilizes a controllable pumping current (CPC) technology, which achieves automatically adjusting output current by feedback mechanism and resizing transfer transistors. The proposed charge pump has been demonstrated in 0.32 µm 3D NAND periphery technology under 3 V power supply. Simulation results show that the output ripple voltage is 1.2 mV at 5 mA load current with 0.1 µF load capacitance. The maximum current drivability and power efficiency is 8 mA and 81% respectively.

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19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming

Cited by 86 publications

References 3 publications

3D NAND Flash Based on Planar Cells

3D NAND Flash Based on Planar Cells

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

A 1.2 mV ripple, 4.5 V charge pump using controllable pumping current technology

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