1T-1C Dynamic Random Access Memory Status, Challenges, and Prospects

Spessot, A.; Oh, H.

doi:10.1109/ted.2020.2963911

Cited by 116 publications

(52 citation statements)

References 46 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, there are regions of dielectric where electric field lines from one wordline can impinge on an adjacent wordline. Such coupling is exacerbated by the fact that the voltage (V PP ) at around 3 V applied to the wordline to turn on the cell transistors is the highest voltage in the chip being charge pumped internally higher than the external power supply voltage [21]. Quite sophisticated simulation can be let loose on this coupling issue [15] but we shall turn to Sakurai [14] to build an insightful model that links the crosstalk peak voltage to the subthreshold leakage of the cell transistors and include the effect of temperature.…”

Section: Capacitive Crosstalkmentioning

confidence: 99%

“…Fig. 1 shows a small section of a generic 6F 2 DRAM cell array up to and including the source and drain junction regions of the cell transistor [21]. Although a DRAM is inherently straightforward, fifty years of development have resulted in wonderful complexity.…”

mentioning

confidence: 99%

“…Therefore, a 3-D drawing approach has been taken to help understand the structure for the purposes of studying the RH disturb. Key features of the structure are: the DRAM cells are located within a retrograde p-well that is isolated from the substrate by a deep n-well (not shown); the SN connecting to one plate of the capacitor is in turn connected to an n-type junction in the p-well; the cell transistor is an nMOS device that over the years has evolved through several structural approaches resulting in the present recessed saddle fin form that enables high drive and low leakage all within a small footprint [21]- [23]. Fig.…”

mentioning

confidence: 99%

See 2 more Smart Citations

On DRAM Rowhammer and the Physics of Insecurity

Walker¹,

Lee

Beery³

2021

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

The dynamic random access memory (DRAM) disturb known as rowhammer (RH) has come to dominate the insecurity of computing systems worldwide. Several studies have concentrated on electron injection from a switching cell select transistor and capture by nearby storage node junctions as being the main mechanism for the effect. This article for the first time looks in-depth at RH from the point of view of both electron injection and capture, and capacitive crosstalk. The absence of such comprehensive studies at the silicon level in the literature can be attributed to its sensitive nature within the industry and highlights the difficulty of DRAM scaling. This review article, therefore, forms a broad foundation to extend understanding of this dangerous disturb mechanism and in so doing provides an informed view on the ability of future DRAM technologies to solve RH once and for all. Index Terms-Crosstalk, dynamic random access memory (DRAM), electron injection, rowhammer (RH). I. INTRODUCTION T HE story of dynamic random access memory (DRAM) is that of the semiconductor industry itself [1], [2]. Fifty years of scaling a field-effect transistor and a capacitor has resulted in DRAM as the "main memory" in all compute systems from cloud servers through laptops to mobile phones. This success makes such systems prone to any security weakness that may lurk within DRAM itself. The DRAM disturb known as rowhammer (RH) has been causing increasing concern since its public unmasking in [3]. It is characterized by corrupted data in cells close to a row that is turned on and off many times between data refresh. Although the actual problem seems to have been known since 2010, and most probably before that within DRAM Research and Development, with some patent applications in 2012, RH was propelled to the forefront of hardware security issues when it was used to gain computer kernel privileges [4]. After ten years from the first inkling of a problem, the RH disturb varies widely between Manuscript

show abstract

Section: Capacitive Crosstalkmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

On DRAM Rowhammer and the Physics of Insecurity

Walker¹,

Lee

Beery³

2021

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…“Memory” device is the most critical component of the modern digital computer. It can be further categorized into dynamic random access memory (DRAM) [ 1 ] and static random access memory (SRAM), [ 2 ] depending on their capability of storing different types of data. Despite their fast write/read speed and long endurance, both DRAM and SRAM are reaching their downscaling limits.…”

Section: Figurementioning

confidence: 99%

Design of Phase‐Change Memory Using Apertureless Scanning Near‐Field Optical Microscopy in the Near‐Infrared Region

Liu

Wang

2020

Physica Rapid Research Ltrs

View full text Add to dashboard Cite

A novel optical secondary storage memory operated in the near‐infrared (NIR) region is developed through the integration of an apertureless scanning near‐field optical microscopy probe with the conventional Ge2Sb2Te5 storage stack. The probe composite and the optical coefficients of the storage media stack, particularly for the indium tin oxide capping layer, are optimized according to a previously developed electromagnetic wave model, and a newly established density functional theory model, respectively. The dielectric core and the metal coating medium of the probe are devised to be glass and barium, respectively, to provide high electric field in the NIR region, while the thickness of the ITO capping layer is chosen to be 3 nm here to provide high optical transmittance simultaneously with exemption of complex fabrication process. The recording operation of the aforementioned optimized device is subsequently simulated by a newly established thermo‐optics model, and its feasibility of achieving ≥Tbit in−2, 108 bits per second, and picojoule energy consumption per bit is theoretically demonstrated.

show abstract

“…The memory elements based on laterally scaled and vertically stacked structures can also significantly increase memory capacity. [2,3] As we advance into the big-data era, the demand for improved performance of computing systems primarily consisting of these two fundamental components, i.e., central processing units (CPUs) and memories, to handle the exponentially growing amount of data is increasing. However, in the conventional von Neumann computing architecture, data executed at the CPU must be frequently moved back and forth to the memory for storage, which can lead to a memory wall or the von Neumann bottleneck, as shown in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

Recent Advancements in Emerging Neuromorphic Device Technologies

Woo

Kim

et al. 2020

Advanced Intelligent Systems

View full text Add to dashboard Cite

The explosive growth of data and information has motivated technological developments in computing systems that utilize them for efficiently discovering patterns and gaining relevant insights. Inspired by the structure and functions of biological synapses and neurons in the brain, neural network algorithms that can realize highly parallel computations have been implemented on conventional silicon transistor‐based hardware. However, synapses composed of multiple transistors allow only binary information to be stored, and processing such digital states through complicated silicon neuron circuits makes low‐power and low‐latency computing difficult. Therefore, the attractiveness of the emerging memories and switches for synaptic and neuronal elements, respectively, in implementing neuromorphic systems, which are suitable for performing energy‐efficient cognitive functions and recognition, is discussed herein. Based on a literature survey, recent progress concerning memories shows that novel strategies related to materials and device engineering to mitigate challenges are presented to primarily achieve nonvolatile analog synaptic characteristics. Attempts to emulate the role of the neuron in various ways using compact switches and volatile memories are also discussed. It is hoped that this review will help direct future interdisciplinary research on device, circuit, and architecture levels of neuromorphic systems.

show abstract

1T-1C Dynamic Random Access Memory Status, Challenges, and Prospects

Cited by 116 publications

References 46 publications

On DRAM Rowhammer and the Physics of Insecurity

On DRAM Rowhammer and the Physics of Insecurity

Design of Phase‐Change Memory Using Apertureless Scanning Near‐Field Optical Microscopy in the Near‐Infrared Region

Recent Advancements in Emerging Neuromorphic Device Technologies

Contact Info

Product

Resources

About