2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Mathew, Sanu; Srinivasan, Suresh; Anders, Mark; Kaul, Himanshu; Hsu, Steven; Sheikh, Farhana; Agarwal, Amit; Satpathy, Sudhir; Krishnamurthy, Ram

doi:10.1109/jssc.2012.2217631

Cited by 171 publications

(74 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Triggering these events comes with a non-negligible energy cost. The most energy-efficient example uses a bistable CMOS circuit forced into in a meta-stable state which then randomly falls into one of the two stable states, generating one random bit 13 . It consumes 3pJ/bit and a circuit area of 4000µm 2 .…”

Section: Introductionmentioning

confidence: 99%

Low-Energy Truly Random Number Generation with Superparamagnetic Tunnel Junctions for Unconventional Computing

et al. 2017

View full text Add to dashboard Cite

Low-energy random number generation is critical for many emerging computing schemes proposed to complement or replace von Neumann architectures. However, current random number generators are always associated with an energy cost that is prohibitive for these computing schemes. In this paper, we introduce random number bit generation based on specific nanodevices: superparamagnetic tunnel junctions. We experimentally demonstrate high quality random bit generation that represents orders-of-magnitude improvements in energy efficiency compared to current solutions. We show that the random generation speed improves with nanodevice scaling, and investigate the impact of temperature, magnetic field and crosstalk. Finally, we show how alternative computing schemes can be implemented using superparamagentic tunnel junctions as random number generators. These results open the way for fabricating efficient hardware computing devices leveraging stochasticity, and highlight a novel use for emerging nanodevices.

show abstract

Section: Introductionmentioning

confidence: 99%

Low-Energy Truly Random Number Generation with Superparamagnetic Tunnel Junctions for Unconventional Computing

et al. 2017

View full text Add to dashboard Cite

show abstract

“…Metastability based TRNG circuits are gaining popularity for their lightweight implementation, high energy efficient and achieving significantly higher bit rate compared to other TRNG circuits [22], [23]. A conventional metastability based TRNG circuit is shown in Figure 4.…”

Section: Testing Bias In True Random Number Generatorsmentioning

confidence: 99%

“…The proposed BIST circuit can be used to uniquely identify the with-in die variation in each chip and enable the appropriate postprocessing module. Circuit calibration techniques use charge dump [24] or digital circuit tuning using additional devices to balance the metastable circuit [23], [26]. An on-chip BIST circuit facilitates in re-calibration of TRNG during powerup and frequent monitoring to detect impact of variations in temperature or device aging.…”

Section: Testing Bias In True Random Number Generatorsmentioning

confidence: 99%

Post-Silicon Validation and Calibration of Hardware Security Primitives

Suresh

Kumar

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

View full text Add to dashboard Cite

Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are gaining significant importance in the field of hardware security. These cryptographic primitives harness randomness from IC fabrication process and on-chip noise respectively; necessitating unconventional post-Silicon (Si) validation techniques. In this work, we present a brief survey of post-Si validation techniques for PUFs and TRNGs, highlighting the importance of testing PUFs resilience against novel attacks and monitoring bias in TRNGs. We also propose novel techniques for monitoring PUFs reliability and measuring bias in TRNGs. The proposed techniques do not only facilitate on-chip calibration for hardware security systems, but can also be used as a countermeasure against fault-attacks.

show abstract

“…Extensive use of analog designs also makes them less attractive in terms of system integration and technology portability. Digital TRNGs offer the advantages of easy integration and lower sensitivity to process, voltage, and temperature variations (PVT variation) over conventional analog designs [4]. For mobile and IoT applications, robustness to environmental variations becomes even more critical.…”

Section: Introductionmentioning

confidence: 99%

“…Previous works have demonstrated digital TRNGs based on metastability [4], [5], oscillator jitter [6]- [10], and other device noise (e.g., time to oxide breakdown [11]). Metastability-based methods using cross-coupled inverters provide excellent operating frequency and power efficiency, but often require extensive design efforts and run-time calibration to remove systematic and temporal mismatch in devices which are sensitive to environmental variations [4], [5]. A soft oxide breakdown-based TRNG provides high entropy random bits but suffers from low performance and low power efficiency due to the nature of the entropy source [11].…”

Section: Introductionmentioning

confidence: 99%

An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations

Yang

Blaauw

Sylvester

2016

IEEE J. Solid-State Circuits

113

View full text Add to dashboard Cite

This paper presents an all-digital true random number generator (TRNG) harvesting entropy from the collapse of two edges injected into one even-stage ring, fabricated in 40 and 180 nm CMOS technologies. A configurable ring and tuning loop provides robustness across a wide range of temperature (−40 • C to 120 • C), voltage (0.6 to 0.9 V), process variation, and external attack. The dynamic tuning loop automatically configures the ring to meet a sufficient collapse time, thereby maximizing entropy. Measured random bits pass all NIST randomness tests across all measured operating conditions and power supply attacks. In 40 nm, the TRNG occupies only 836 µm 2 and consumes 23 pJ/bit at nominal 0.9 V and 11 pJ/bit at 0.6 V.

show abstract

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Cited by 171 publications

References 12 publications

Low-Energy Truly Random Number Generation with Superparamagnetic Tunnel Junctions for Unconventional Computing

Low-Energy Truly Random Number Generation with Superparamagnetic Tunnel Junctions for Unconventional Computing

Post-Silicon Validation and Calibration of Hardware Security Primitives

An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations

Contact Info

Product

Resources

About