2.4 GHz CMOS digitally programmable power amplifier for power back-off operation

Abstract

This paper presents the simulation results of a linear, fully integrated, two-stage digitally programmable 130 nm CMOS power amplifier (PA) operating at 2.4 GHz. Its power stage is composed of a set of amplifying cells which can be enabled or disabled independently by a digital control circuit. All seven operational modes are univocal in terms of 1 dB output compression point (OCP1dB), saturated output power (PSAT) and power gain at 2.4 GHz. The lowest power mode achieves an 8.1 dBm PSAT, a 13.5 dB power gain and consumes 171 mW DC power (PDC) at an OCP1dB of 6 dBm, whereas the highest power mode reaches an 18.9 dBm PSAT and a 21.1 dB power gain and consumes 415 mW PDC at an OCP1dB of 18.2 dBm.