2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Abstract

Dedicated, after acceptance and publication, in memory of the late Vassos Soteriou. For the first time, we leverage the 2.5D interposer technology to establish system-level security in the face of hardware-and software-centric adversaries. More specifically, we integrate chiplets (i.e., third-party hard intellectual property of complex functionality, like microprocessors) using a security-enforcing interposer. Such hardware organization provides a robust 2.5D root of trust for trustworthy, yet powerful and flexible, computation systems. The security paradigms for our scheme, employed firmly by design and construction, are: 1) stringent physical separation of trusted from untrusted components, and 2) runtime monitoring. The system-level activities of all untrusted commodity chiplets are checked continuously against security policies via physically separated security features. Aside from the security promises, the good economics of outsourced supply chains are still maintained; the system vendor is free to procure chiplets from the open market, while only producing the interposer and assembling the 2.5D system oneself. We showcase our scheme using the Cortex-M0 core and the AHB-Lite bus by ARM, building a secure 64-core system with shared memories. We evaluate our scheme through hardware simulation, considering different threat scenarios. Finally, we devise a physical-design flow for 2.5D systems, based on commercial-grade design tools, to demonstrate and evaluate our 2.5D root of trust.

Hardware Security For and Beyond CMOS Technology

“…For example, the NAND-NOR-XOR primitive of [50] would incur 5.5× power, 1.6× delay, and 4× area cost compared to a regular NAND gate. 4 In contrast, the work in [184] report on average only 25% power cost, 15% delay cost, and 43% area savings compared to regular 2D gates.…”

“…Trojan detection at runtime, however, can benefit from 3D and 2.5D integration. That is because related security features can be implemented separately using a trusted fabrication process and integrated/stacked later on with the commodity chip(s) to be monitored [4,81]; see also the discussion on data security below. 4.2.5 Confidentiality and Integrity of Hardware: PUFs.…”

“…Within the realm of cybersecurity in general, hardware security in particular is concerned about achieving security and trust directly within the underlying electronics. Therefore, hardware security seeks to build up, e.g., so-called root of trust (RoT) schemes for isolation and attestation of computation [2][3][4], or other hardware primitives and protection schemes.…”

“…Such "breadand-butter" attacks are conducted mainly at the software level. Cryptography represents the most commonly applied protection scheme, while many hardware security features have been proposed and implemented as well, e.g., RoT architectures [2][3][4] or hardware crypto modules [6] and true random number generators (TRNGs) to support the latter. However, if not designed and implemented carefully, such security features become prone to hardware-centric attacks, e.g., see [7][8][9][10][11]; such attacks are discussed below.…”

Chiplet Heterogeneous Integration Technology—Status and Challenges

“…Overall, since chiplets could provide customizability and optimizability in multiple dimensions (such as the yield and cost), it would be widely applied in more fields [33,34]. With the rapid rise of open-source ecology and agile development [35] in the chip field, chiplet approach would become the mainstream technology for chip development in the future.…”