2-D-Nonlinear Electrothermal Model for Investigating the Self-Heating Effect in GAAFET Transistors

Belkhiria, Maissa; Echouchene, Fraj; Jaba, Nejeh; Bajahzar, Abdullah; Belmabrouk, Hafedh

doi:10.1109/ted.2020.3048919

Cited by 20 publications

(2 citation statements)

References 34 publications

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“…To verify the accuracy of simulation proc MOSFET, shown in Figure 4a, with 20 nm channel length, 1nm gate oxid nanowire radius is simulated. In Figure 4b, the simulated results are co perimental data reported in [31], and good agreement is achieved.…”

Section: Simulationsupporting

confidence: 63%

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

et al. 2021

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In this paper, an innovative vertical MOSFET based on through-oxide via (TOV) technology is proposed for silicon-on-insulator (SOI)-based monolithic 3-D ICs. The proposed vertical MOSFET is investigated numerically. It was found that SOI can effectively reduce the parasitic capacitance, leakage current, power consumption, as well as suppress the pulse current interference of the substrate. The simulated results indicate that the proposed MOSFET possesses excellent characteristics in saturation current over 1500 μA, sub-threshold swing of 69 mV/dec, and on/off current ratio of 1.28 × 1011. Moreover, as temperature is a critical factor for the performance degradation of semiconductor devices, electrothermal simulations are conducted to predict the influence of the self-heating effect on device characteristics. The results show that device characteristics slightly deteriorate, but can still acceptable in their applications.

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Section: Simulationsupporting

confidence: 63%

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

et al. 2021

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“…The solution of the equation is an approach to the real solution. Previously, we analyzed the self-heating effect in GAAFETs [50] using the finite element method. The finite element discretization has been used to tackle the effect of Joule heating in a conductive-bridge random-access memory (CBRAM) for the single-phase-lag heat conduction model [51].…”

Section: Introductionmentioning

confidence: 99%

Investigation of Trap Density Effect in Gate-All-Around Field Effect Transistors Using the Finite Element Method

Belkhiria,

Aouaini,

A. Aldaghfag

et al. 2023

Electronics

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Trap density refers to the density of electronic trap states within dielectric materials that can capture and release charge carriers (electrons or holes) in a semiconductor channel, affecting the transistor’s performance. This study aims to investigate the influence of trap density on the electrothermal behavior of nanowire gate-all-around GAAFET devices. The numerical solution of Poisson’s equations and continuity equations, coupled with the heat conduction model, has been used to predict the temperature inside the GAAFET device. The finite element method has been used to discretize the semiconductor equations. Investigations have been carried out on a number of physical and geometric parameters, such as oxide thickness, nanowire radius, and gate length. Their effects on output characteristics and device temperature have been discussed. A thinner oxide thickness, lower device radius, and longer channel length led to a higher current flow. Results also reveal that high trap densities can have significant impacts on the degradation of electronic devices, particularly in the context of semiconductor devices like transistors.

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Nano-heat Transfer in GAAFET Transistor Using Single-Phase-Lag Model

Belkhiria

Echouchene

Jaba

2021

Lecture Notes in Mechanical Engineering

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2-D-Nonlinear Electrothermal Model for Investigating the Self-Heating Effect in GAAFET Transistors

Cited by 20 publications

References 34 publications

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

Investigation of Trap Density Effect in Gate-All-Around Field Effect Transistors Using the Finite Element Method

Nano-heat Transfer in GAAFET Transistor Using Single-Phase-Lag Model

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