2$\,\times\,$2 Switch Matrix for WiMAX Relay Station Applications

Voudouris, Konstantinos; Αθανασόπουλος, Νικόλαος; Meir, A.; Manor, D.; Tsiakas, Panagiotis; Georgas, Iraklis; Petropoulos, Ioannis; Agapiou, George

doi:10.1109/lmwc.2011.2158532

Cited by 8 publications

(2 citation statements)

References 4 publications

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“…2,4 The double-pole double-throw (DPDT) switch matrix is a widely used component to route RF signals between multiinputs and multioutputs. 5-8 RF switch matrices have been implemented by silicon-on-insulator (SOI), 5 PIN-diode, 6 and SiGe. 7 These processes have excellent RF performance because of high substrate resistance and small parasitic capacitance.…”

Section: Introductionmentioning

confidence: 99%

High isolation and high linearity double‐pole double‐throw CMOS switch matrix for Ka‐band wireless transceiver front‐end IC

Park

Lee

Kim

et al. 2018

Micro & Optical Tech Letters

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This letter proposes a double‐pole double‐throw (DPDT) switch with high isolation and high linearity using a 65‐nm CMOS process. To improve the isolation, resonant inductors are employed for the core switches, which are composed of a single‐stacked NMOS with gate‐body floating techniques. And, the switch is controlled by a cross‐biasing technique to increment the power linearity. The active circuits are designed separately from the passive elements to reduce the interference. The core area of the proposed switch excluding all of the pads is 380 × 300 μm2. The minimum insertion loss is 2.57 dB at 23 GHz and maximum isolation is 39.7 dB at 26 GHz, respectively. The third‐order intermodulation intercept point (IIP3) is 37 dBm at 28 GHz.

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Section: Introductionmentioning

confidence: 99%

High isolation and high linearity double‐pole double‐throw CMOS switch matrix for Ka‐band wireless transceiver front‐end IC

Park

Lee

Kim

et al. 2018

Micro & Optical Tech Letters

View full text Add to dashboard Cite

show abstract

“…111 RF switch matrixes for MIMO application have been reported based on various processes and technology nodes previously, including GaAs JFET [75], 0.5 μm pHEMT process [76], PIN diode [77], 0.13 μm CMOS [78], 0.12 μm triple-well CMOS [79], and [80]- [82]. However, all these designs are limited within dc to 12 GHz frequency range.…”

Section: Port1mentioning

confidence: 99%