2 × VDD output buffer with 36.4% slew rate improvement using leakage current compensation

Abstract

A 2 × VDD output buffer using leakage current compensation is demonstrated. With the proposed leakage current compensation circuit, the SR (slew rate) is improved 36.4-101.89% based on onsilicon measurement results given different VDDIO (1.0/1.2/1.8 V) and temperatures (from 0 to 100°C). The data rate is 510/630/ 400 MHz for VDDIO at 1.8/1.2/1.0 V, respectively. Moreover, the reliability problem, the gate oxide overstress and the hot carrier degradation is avoided. The proposed design is implemented using a typical 90 nm CMOS process. The active area is 0.425 × 0.0563 mm. The SR is measured in the range from 0.766 to 2.585 V/ns.

Low‐leakage track‐and‐hold buffer in 130‐nm CMOS with open‐gate FET bias

“…Several authors have reported on techniques for reducing switch leakage [2][3][4][5], but few on circuit solutions for gate leakage reduction. Several authors [6][7][8] have presented options for minimizing gate leakage but with limited application to high precision track-andhold buffers. Although the industry introduced high-K gate dielectrics to address this gate leakage issue, it remains a limitation at advanced nodes.…”