20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS

Krishnamurthy, Harish K.; Vaidya, Vaibhav; Weng, Sheldon; Ravichandran, Krishnan; Kumar, Pankaj; Kim, Stephen; Jain, Rachna; Matthew, George E.; Tschanz, Jim; De, Vivek

doi:10.1109/isscc.2017.7870398

Cited by 22 publications

(21 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, off-chip VRs have slow response times and, hence, cannot support fine-grained DVS. There has been a great deal of progress on fully integrated buck VRs, thanks to on-die/in-package inductors and new magnetic materials [24]- [26]. Operating at a frequency of tens or hundreds of megahertz, fully integrated buck VRs come with fast response times and promises for efficient local power delivery and fine-grain DVFS.…”

Section: A Overview Of Voltage Regulatorsmentioning

confidence: 99%

“…Operating at a frequency of tens or hundreds of megahertz, fully integrated buck VRs come with fast response times and promises for efficient local power delivery and fine-grain DVFS. However, integrating high-Q power inductors to support high current density with low loss is still a major challenge [24]- [26]. Compared to their off-chip counterparts, on-chip buck VRs incur more conduction and switching losses, leading to lower efficiency, especially at light loads.…”

Section: A Overview Of Voltage Regulatorsmentioning

confidence: 99%

See 1 more Smart Citation

Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation

Zhan

Chen

Sánchez-Sinencio

2019

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

This work is based on the vision that the ultimate power integrity and efficiency may be best achieved via a heterogeneous chain of voltage processing starting from onboard switching voltage regulators (VRs), to on-chip switching VRs, and finally to networks of distributed on-chip linear VRs. As such, we propose a heterogeneous voltage regulation (HVR) architecture encompassing regulators with complimentary characteristics in response time, size, and efficiency. By exploring the rich heterogeneity and tunability in HVR, we develop systematic workload-aware power management policies to adapt heterogeneous VRs with respect to workload change at multiple temporal scales to significantly improve system power efficiency while providing a guarantee for power integrity. The proposed techniques are further supported by hardware-accelerated machine learning (ML) prediction of nonuniform spatial workload distributions for more accurate HVR adaptation at fine time granularity. Our evaluations based on the PARSEC benchmark suite show that the proposed adaptive three-stage HVR reduces the total system energy dissipation by up to 23.9% and 15.7% on average compared with the conventional static two-stage voltage regulation using off-chip and on-chip switching VRs. Compared with the three-stage static HVR, our runtime control reduces system energy by up to 17.9% and 12.2% on average. Furthermore, the proposed ML prediction offers up to 4.1% reduction of system energy.

show abstract

Section: A Overview Of Voltage Regulatorsmentioning

confidence: 99%

Section: A Overview Of Voltage Regulatorsmentioning

confidence: 99%

Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation

Zhan

Chen

Sánchez-Sinencio

2019

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…Such a mixed-voltage system typically requires additional bill-of-material (BOM) cost, board/package area and I/O pins, to support multiple voltage domains with the conventional off-chip regulators [2]. Since most SoCs are area and cost sensitive, especially for the portable IoT electronics with small form factors, the full integration of voltage regulators on the die has received increasing interests [4][5][6][7]. Unlike on-board regulation, integrated regulation has the following appealing features: (1) Simplifying the board/package and external complexity;…”

Section: Introductionmentioning

confidence: 99%

Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Wen

Xiao

Chen

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

The conventional on-chip spiral inductor consumes a significant top-metal routing area, thereby preventing its popularity in many on-chip applications. Recently through-silicon-via (TSV) based inductor (also known as TSV-inductor) with a magnetic core has been proved to be a viable option for the on-chip DC-DC converter. The operating conditions of these inductors play a major role in maximizing the performance and efficiency of the DC-DC converter. However, there is a critical need to study the design and optimization details of magnetic core TSV-inductors with the unique 3D structure embedding magnetic core. This paper aims to provide a clear understanding of the modeling details of a magnetic core TSV-inductor and a design and optimization methodology to assist efficient inductor design. Moreover, a machine learning assisted model combining physical details and artificial neural network (ANN) is also proposed to extract the equivalent circuit to further facilitate DC-DC converter design. Experimental results show that the optimized TSV-inductor with the magnetic core and air-gap can achieve inductance density improvement of up to 7.7 × and quality factor improvements of up to 1.6 × for the same footprint compared with the TSV-inductor without a magnetic core. For on-chip DC-DC converter applications, the converter efficiency can be improved by up to 15.9% and 6.8% compared with the conventional spiral and TSV-inductor without magnetic core, respectively.

show abstract

“…between the package and the microprocessor die, due to the reduced total input current. However, these benefits come at the cost of substantial chip area being sacrificed for the IVRs' components [7], [8] and / or highly challenging realization of chip-integrated inductors, e.g., due to the need of complex Through Silicon Vias (TSVs) [9] and additional Back End Of Line (BEOL) post-processing steps [8]. In addition, the chip technology node used for the microprocessor defines stringent design constraints, which considerably limit the flexibility of the converter design.…”

Section: Introductionmentioning

confidence: 99%

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Bezerra

Krismer

Kolar

et al. 2020

IEEE Open J. Power Electron.

View full text Add to dashboard Cite

Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB-and inductorbased four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1 % at an output power of Pout = 640 mW and a switching frequency of fs = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at fs = 50 MHz and Pout ∈ [500 mW, 600 mW]; at Pout = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

show abstract

20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS

Cited by 22 publications

References 2 publications

Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation

Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation

Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Contact Info

Product

Resources

About