200 MHz video compression macrocells using low-swing differential logic

Matsui, M.; Hara, Hiroyuki; Seta, K.; Uetani, Yoshiharu; Kim, Lee-Sup; Nagamatsu, T.; Shimazawa, T.; Mita, Shiro; Otomo, G.; Oto, T.; Watanabe, Yoshinori; Sano, Fumihiko; Chiba, A.; Matsuda, K.; Sakurai, Takayasu

doi:10.1109/isscc.1994.344720

Cited by 40 publications

(13 citation statements)

References 2 publications

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“…12 and for clock frequency of 110 MHz, the share subexpressions reduces the dynamic power by 22% compared to the CSD-based DCT architecture and by 9% compared to the Xilinx's embedded multipliers-based DCT design . Furthermore, these values are compared favorably with other works as for example 11.5 mW at 2V design and 40 MHz in [36] or 3.94 mw at 1.6 V design and 40 MHz in [27].…”

Section: Power Analysismentioning

confidence: 83%

Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression

Jridi

Alfalou

2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Abstract. The Discrete Cosine Transform (DCT)-based image compression is widely used in today's communication systems. Significant research devoted to this domain has demonstrated that the optical compression methods can offer a higher speed but suffer from bad image quality and a growing complexity. To meet the challenges of higher image quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI architecture of the DCT algorithm and an efficient quantization technique. Our approach is, firstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a reconfigurable quantization method is presented to effectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and comparisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement.

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Section: Power Analysismentioning

confidence: 83%

Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression

Jridi

Alfalou

2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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“…The SAFF was initially seen in StrongArm110 and is now widely used in high-speed systems [13]. It is composed of a very fast pre-charged sense-amplifier stage followed by a set-reset latch.…”

Section: Proposed Photon-emitting Sequential Circuitsmentioning

confidence: 99%

Optical Failure Analysis Technique in Deep Submicron CMOS Integrated Circuits

Kim¹,

Lee²,

Lee³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flipflop based on a sense amplifier and a photon-emitting device. This method can be used even with deepsubmicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the spectrum. The effectiveness of our approach has been proved by the failure analysis of a prototype designed and fabricated in 0.18 μm CMOS process.Index Terms-Circuit testing, deep submicron CMOS technology, failure analysis, photon emission, picosecond imaging circuit analysis (PICA)

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“…This executes twodimensional 8x8 HDTV-resolution video compression and decompression. Original design was made for an n-well technology [5]. We have modified the well/substratecontact layout for the VT scheme as follows.…”

Section: Dct Experimental Resultsmentioning

confidence: 99%

“…High-speed but noise-sensitive circuits are employed in the DCT macro such as small-swing differential dynamic pass-transistor logic with sense-amplifying pipeline flip-flop [5], and various memories such as ROM's and SRAM's.…”

Section: Dct Experimental Resultsmentioning

confidence: 99%

Substrate noise influence on circuit performance in variable threshold-voltage scheme

Kuroda¹,

Fujita²,

Mita³

et al.

Proceedings of 1996 International Symposium on Low Power Electronics and Design

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-This paper investigates substrate noise influence on circuit performance in a variable thresholdvoltage scheme (VT scheme) where threshold voltage is dynamically varied by substrate-bias control to reduce active power dissipation. It is experimentally examined that substrate-bias can be controlled stably with very few substrate-contacts. Measured tracking jitter of a delaylocked loop implemented by interconnections in an 8mm-square gate array does not degrade even when substratecontacts are removed except for one at every strip of p-sub and n-well. A 2mm-square discrete cosine transform core processor with no substrate-contact except in its periphery operates at supply voltages from 1.3V to above 3V even though it employs small-swing differential dynamic pass-transistor logic.No performance degradation nor latchup is observed in these chips even when 100kΩ resistance is added to the substrate. These experimental results demonstrate noise immunity of the VT scheme, and indicate the possibility that the VT scheme can be applied to existing macro design easily.

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200 MHz video compression macrocells using low-swing differential logic

Cited by 40 publications

References 2 publications

Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression

Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression

Optical Failure Analysis Technique in Deep Submicron CMOS Integrated Circuits

Substrate noise influence on circuit performance in variable threshold-voltage scheme

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