21.1 A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme

Zhang, Huajun; Zhang, Mingshuang; Chen, Mengying; Admiraal, Arthur; Zhang, Miao; Berkhout, Marco; Fan, Qinwen

doi:10.1109/isscc49657.2024.10454288

2024 IEEE International Solid-State Circuits Conference (ISSCC) 2024

DOI: 10.1109/isscc49657.2024.10454288

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21.1 A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme

Huajun Zhang,

Mingshuang Zhang,

Mengying Chen

et al.

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Cited by 2 publications

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A 121.7-dB DR and -109.0-dB THD+N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells

Zhang,

Chen

et al. 2024

IEEE J. Solid-State Circuits

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A 121.7-dB DR and -109.0-dB THD+N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells

Zhang,

Chen

et al. 2024

IEEE J. Solid-State Circuits

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A 0.00055% THD + N Class-D Audio Amplifier With Capacitive Feedforward PWM and Wide-Band Aliasing Reduction

Zhou,

Tang

et al. 2024

IEEE J. Solid-State Circuits

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21.1 A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme

Cited by 2 publications

References 6 publications

A 121.7-dB DR and -109.0-dB THD+N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells

A 121.7-dB DR and -109.0-dB THD+N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells

A 0.00055% THD + N Class-D Audio Amplifier With Capacitive Feedforward PWM and Wide-Band Aliasing Reduction

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