21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS

Yoo, Taegeun; Jung, Yun-Hwan; Yeoh, Hong Chang; Kim, Yong Sin; Kang, Sung‐Mo; Baek, Kwang‐Hyun

doi:10.1109/isscc.2014.6757471

Cited by 9 publications

(13 citation statements)

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“…More recently, a new approach to replace the P2AM and linear DAC with a sign weighted nonlinear DAC (NLDAC) have been proposed to achieve both low power and high performance [4], [27], [28]. FIGURE 2 (c) shows the basic structure of the NLDAC-based DDFS, where a nonlinear sign weighted DAC directly converts the output of the PACC to the desired sign wave.…”

Section: Design Of the Low Power Ddfs A Conventional Ddfs Methodmentioning

confidence: 99%

“…Because the NLDAC can be simply implemented with a thermometer decoder (decoding logic) and a nonlinear weighted DAC (current sources), its power consumption and design complexity are much less than the digital and analog mappers in the previous DDFS structures. From the former NLDAC-based DDFS proposed by the author of this paper [4], the design technique to significantly simplify the decoding logic in the NLDAC has been introduced. More specifically, the general operation of the NLDAC that divides the current source into coarse and fine phases to reduce the operating complexity has been focused.…”

Section: Design Of the Low Power Ddfs A Conventional Ddfs Methodmentioning

confidence: 99%

“…Owing to these advantages, the DDFS method has been used in a wide range of applications such as radar, military equipment, medical devices, and aircraft [1]- [3]. However, the DDFS method has the critical drawback in high power consumption, causing the difficulty of using it in portable (battery-powered) devices [4], [5]. Since the DDFS conventionally uses readonly-memory (ROM) for signal generation, the required ROM size gets also significantly increased as the performance requirements of the synthesizer increases.…”

Section: Introductionmentioning

confidence: 99%

“…To resolve this problem, active researches on the DDFS method and its hardware design have been steadily conducted, and the recent research results show that the power consumption level of DDFS can be lowered to the usage in portable devices. For example, the recent work [4] of the low power direct digital frequency synthesizer (LP-DDFS) consumes less than 130mW, which is much smaller than common mobile AP cores. Having the potential for lowering additional power consumption from the previous LP-DDFS [4], a new advanced LP-DDFS architecture is proposed in this paper.…”

Section: Introductionmentioning

confidence: 99%

“…For example, the recent work [4] of the low power direct digital frequency synthesizer (LP-DDFS) consumes less than 130mW, which is much smaller than common mobile AP cores. Having the potential for lowering additional power consumption from the previous LP-DDFS [4], a new advanced LP-DDFS architecture is proposed in this paper. In the new LP-DDFS, CML-based circuit design is replaced with CMOS-based circuit through the theoretical and practical analysis of the dynamic and static power characteristics.…”

Section: Introductionmentioning

confidence: 99%

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Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

et al. 2020

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Due to the advantages of fast frequency shifting, continuous phase shifting, fine frequency resolution, large bandwidth, and excellent spectral purity, the direct digital frequency synthesis (DDFS) technique is attracting more attention than ever before. Although the DDFS suffer from high power consumption, recent researches on the development of the low power DDFS (LP-DDFS) increases the feasibility of applying the DDFS to portable devices. To further accelerate the use of LP-DDFS, a new LP-DDFS design to significantly improve power efficiency is proposed and analyzed in this paper. In the new design, the dominant spur by truncation errors causing performance degradation has been also thoroughly considered. Since the existing dithering techniques for the truncation error problems can cause the additional performance degradation due to the side effects such as frequency offset and SNDR deterioration, an enhanced dithering technique is also proposed in this paper. The proposed technique includes a frequency compensation circuit and thus minimizes the truncation errors in the LP-DDFS with the minimal additional power consumption and SNDR degradation. Both theoretical and experimental analysis are conducted to verify the proposed design, where a prototype chip is fabricated and measured. INDEX TERMS Direct digital frequency synthesizer (DDFS/DDS), dithering scheme, high spuriousfree dynamic range (SFDR), low power design, Phase accumulator (PACC), pseudo-random binary sequence (PRBS).

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Section: Design Of the Low Power Ddfs A Conventional Ddfs Methodmentioning

confidence: 99%

Section: Design Of the Low Power Ddfs A Conventional Ddfs Methodmentioning

confidence: 99%