22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI

Abstract

5 contributed to this work while employed by Fujitsu Laboratories of America, Sunnyvale, CA Integrated photonic interconnect technology is free from the bandwidth-distance limitation that intrinsically exists in electrical interconnects, promising a disruptive alternative for next-generation scalable data centers. Silicon photonic platforms have been reported based on monolithic and hybrid integration. Monolithic systems mitigate integration overhead but require compromise in either electronic or photonic device performance [1,2]. Hybrid integration allows for independent process selection for each device so that overall system can potentially achieve the best performance [3]. This paper presents a hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology. A pseudo-differential driver with pre-emphasis enables an 800MHz bandwidth (BW) carrier-injection ring modulator to operate at 25Gb/s with power efficiency of 2.9pJ/b. A TIA implements two BW-enhancement techniques: a regulated-cascode (RGC) input stage with shunt-shunt feedback and T-coil inductive peaking, and a hybrid offset calibration, achieving 25Gb/s with power efficiency of 2.0pJ/b and a sensitivity of -8.0dBm OMA.The transceiver structure and block diagram is shown in Fig. 22.2.1. The face-down driver/TIA chip is partly bonded to the face-up photonic chip via 50μm-pitch low-parasitic micro bumps and partly bonded to the package build-up substrate via C4 bumps enabling power supply and electrical signal input/output. The E-O interface is designed to be placed adjacent to CPU or memory within a package so that high-speed electrical signaling can be kept within a few centimeters and power-hungry loss-compensation circuits such as DFE can be eliminated. Unlike the hybrid integration in [3] that requires power delivery to face-up chips by upside wire springs and cooling from below, our assembly applies established flip-chip powering and cooling techniques.We implement a forward-biased PIN ring modulator ( Fig. 22.2.2), which has an optical BW of 20GHz limited by photon lifetime and an electrical BW of 800MHz due to large junction capacitance. The large junction capacitor enables sufficient carrier injection for changing the refractive index of optical waveguides to achieve reasonable modulation depth with low driving voltage. The modulator contains phase shifters based on a side-wall grating waveguide, which is easier to control in etching process and thus expected to have a higher yield than a rib waveguide [4]. The transmission spectrum is measured at various DC bias voltages, showing resonant peak frequency of 1556nm at 0.9V bias and an extinction ratio (ER) of 8dB with only 0.2V voltage change. A small signal model is derived by fitting the measured optical frequency response, where R S =50Ω C F = 2.2pF R F = 820Ω at 0.9V bias voltage. The required gain boost at f b /2 for 25Gb/s (corresponding to 12.5GHz) is 12 to 30dB depending on modulator va...

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