2008 IEEE International Electron Devices Meeting 2008
DOI: 10.1109/iedm.2008.4796769
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22 nm technology compatible fully functional 0.1 &#x03BC;m<sup>2</sup> 6T-SRAM cell

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Cited by 26 publications
(25 citation statements)
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“…Recently, IBM has released information about the upcoming 22 nm technology node, which features an SRAM with areal density of 0.1 µm 2 [ 23 ]. The SRAM has dimensions of 0.18 µm " 0.554 µm and is shown in Fig.…”
Section: Seu Sensitivity Of Modern Soi Sramsmentioning
confidence: 99%
“…Recently, IBM has released information about the upcoming 22 nm technology node, which features an SRAM with areal density of 0.1 µm 2 [ 23 ]. The SRAM has dimensions of 0.18 µm " 0.554 µm and is shown in Fig.…”
Section: Seu Sensitivity Of Modern Soi Sramsmentioning
confidence: 99%
“…DP technologies include numerous process variations, including spacer technologies, Litho-Etch-Litho-Etch (LELE), and Litho-Freeze-Litho-Etch (LFLE), which satisfy the target feature sizes and geometries. In fact, recent device work 1,2 has shown the ability of DP to supersede EUVL from a device scaling and performance point of view. This new "lithographic" approach represents a wholesale change in scaling for the industry, which is being driven far more by processing than by introducing new lithography hardware.…”
Section: Introductionmentioning
confidence: 99%
“…High index immersion remains a potential lithographic solution to further complement and extend the applications of DP technologies to smaller dimensions or relaxing k 1 . 3 The high-index current status and development challenges are discussed below.…”
Section: Introductionmentioning
confidence: 99%
“…The implementation of EUV lithography in the next five years is unlikely due to economic factors. Double patterning lithography (DPL) is a technology that has been implemented by the industry and has already shown the proof of concept for the 22nm node [3] .…”
Section: Introductionmentioning
confidence: 99%
“…The implementation of EUV lithography in the next five years is unlikely due to economic factors. Double patterning lithography (DPL) is a technology that has been implemented by the industry and has already shown the proof of concept for the 22nm node [3] .This technique while expensive is the only current path forward for scaling with no fundamental showstoppers for the 32nm and 22nm nodes. Double exposure lithography (DEL) is being proposed as a cost mitigating approach to advanced lithography.…”
mentioning
confidence: 99%