23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor

Pyo, Jungyul; Shin, Youngmin; Lee, Hoi-Jin; Bae, Sung-Il; Kim, Minsu; Kim, Kwang Il; Shin, Keun Wook; Kwon, Yohan; Oh, Heungchul; Lim, Jae‐Young; Lee, Dong‐Wook; Lee, Jong-Ho; Hong, In-Pyo; Chae, Kyungkuk; Lee, Heon-Hee; Lee, Sungwook; Song, Sunghoon; Kim, Chung Hee; Park, Jin-Soo; Kim, Hee‐Soo; Yun, Seokho; Cho, Uk-Rae; Son, Jae Cheol; Park, Sungho

doi:10.1109/isscc.2015.7063105

Cited by 11 publications

(3 citation statements)

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“…18.5 mm 2 (S6). For comparison, from [37], [45] We derive a worst-case upper bound for the power consumption of our architecture by assuming 100 % toggle rate on all logic cells and 50/50 % read/write activity at each memory macro. The overall power envelope is 6.1 W, 99.8 % of which is dynamic power (S6).…”

Section: A Hardware Synthesis and Powermentioning

confidence: 99%

A RISC-V in-network accelerator for flexible high-performance low-power packet processing

Girolamo

Kurth

Calotoiu

et al. 2021

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)

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The capacity of offloading data and control tasks to the network is becoming increasingly important, especially if we consider the faster growth of network speed when compared to CPU frequencies. In-network compute alleviates the host CPU load by running tasks directly in the network, enabling additional computation/communication overlap and potentially improving overall application performance. However, sustaining bandwidths provided by next-generation networks, e.g., 400 Gbit/s, can become a challenge. sPIN is a programming model for in-NIC compute, where users specify handler functions that are executed on the NIC, for each incoming packet belonging to a given message or flow. It enables a CUDA-like acceleration, where the NIC is equipped with lightweight processing elements that process network packets in parallel. We investigate the architectural specialties that a sPIN NIC should provide to enable high-performance, low-power, and flexible packet processing. We introduce PsPIN, a first open-source sPIN implementation, based on a multi-cluster RISC-V architecture and designed according to the identified architectural specialties. We investigate the performance of PsPIN with cycle-accurate simulations, showing that it can process packets at 400 Gbit/s for several use cases, introducing minimal latencies (26 ns for 64 B packets) and occupying a total area of 18.5 mm 2 (22 nm FDSOI).

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Section: A Hardware Synthesis and Powermentioning

confidence: 99%

A RISC-V in-network accelerator for flexible high-performance low-power packet processing

Girolamo

Kurth

Calotoiu

et al. 2021

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)

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“…These devices contain two 100 Gbit Ethernet ports, a Gen4 16× PCIe port and an additional ARM subsystem with up to 16 A72 64 bit cores with 1 MiB shared L2 cache per 2 cores, and 6 MiB shared L3 lastlevel cache. From [31,32] it can be inferred that one A72 dual-core tile occupies around 5.6 mm 2 in 22 nm technology, and hence a full 16 core configuration amounts to around 51 mm 2 . Hence, with an overall complexity of 23.5 mm 2 , we observe that the analyzed parameterization of the proposed accelerator only occupies about 45% of the area budget allocated for the processing subsystem in this related commercial device.…”

Section: Circuit Complexity and Power Estimationsmentioning

confidence: 99%

Network-accelerated non-contiguous memory transfers

Girolamo

Taranov

Kurth

et al. 2019

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

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Applications often communicate data that is non-contiguous in the send-or the receive-buffer, e.g., when exchanging a column of a matrix stored in row-major order. While non-contiguous transfers are well supported in HPC (e.g., MPI derived datatypes), they can still be up to 5x slower than contiguous transfers of the same size. As we enter the era of network acceleration, we need to investigate which tasks to offload to the NIC: In this work we argue that non-contiguous memory transfers can be transparently networkaccelerated, truly achieving zero-copy communications. We implement and extend sPIN, a packet streaming processor, within a Portals 4 NIC SST model, and evaluate strategies for NIC-offloaded processing of MPI datatypes, ranging from datatype-specific handlers to general solutions for any MPI datatype. We demonstrate up to 10x speedup in the unpack throughput of real applications, demonstrating that non-contiguous memory transfers are a first-class candidate for network acceleration.

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“…The natural progression towards the emergence of the heterogeneous SoC as the main computing platform across many application domains [21,24,26] is a consequence of the end of Dennard's ideal CMOS scaling. Facing the inability of continuing to scale down supply voltages, the designers of integrated circuits have made two consecutive moves.…”

Section: Introductionmentioning

confidence: 99%

Invited - The case for embedded scalable platforms

Carloni

2016

Proceedings of the 53rd Annual Design Automation Conference

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Heterogeneous system-on-chip (SoC) architectures are emerging as a fundamental computing platform across a variety of domains, from mobile to cloud computing. Heterogeneity, however, increases design complexity in terms of hardware-software interactions, access to shared resources, and diminished regularity of the design. Embedded Scalable Platforms are a novel approach to SoC design and programming that addresses these design-complexity challenges by combining an architecture and a methodology. The flexible socketed architecture simplifies the integration of heterogeneous components by balancing regularity and specialization. The companion methodology raises the level of abstraction to system-level design, thus promoting closer collaboration among software programmers and hardware engineers. The architecture is supported by a scalable communication infrastructure. The methodology leverages compositional design-space exploration with high-level synthesis. The case for Embedded Scalable Platforms is made based on experiments on the development of various full-system prototypes and experience in teaching these concepts in a new graduate course.

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23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor

Cited by 11 publications

References 1 publication

A RISC-V in-network accelerator for flexible high-performance low-power packet processing

A RISC-V in-network accelerator for flexible high-performance low-power packet processing

Network-accelerated non-contiguous memory transfers

Invited - The case for embedded scalable platforms

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