23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme

Kim, Dongkyun; Park, Minsu; Jang, Sungchun; Song, Jianwei; Chi, Hankyu; Choi, Geun-Ho; Choi, Sunmyung; Kim, Jaeil; Kim, Changhyun; Kim, Kyungwhan; Song, Seonghwi; Kim, Yongmi; Lee, Dong Uk; Lee, Jaein; Kim, Dae-Suk; Kwon, Kihun; Han, Minsik; Choi, Byeongchan; Kim, Hongjung; Ku, Sanghyun; Kim, Y.; Kim, Jong-Sam; Kim, Sanghui; Seo, Young-Suk; Oh, Seung-Wook; Im, Dain; Kim, Haksong; Choi, Jong‐Min; Chung, Jihoon; Lee, Changhyun; Lee, Yong-Sung; Cho, Joohwan; Chun, Junhyun; Oh, Jae‐Eung

doi:10.1109/isscc.2019.8662320

Cited by 17 publications

(4 citation statements)

References 2 publications

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“…However, there exists a need to expand this research to the latest generation, such as DDR5. DDR5 DRAM undergoes a more aggressive scaling process, aiming for increased density and larger bandwidth [ 84 , 85 , 86 , 87 ]. The increased scaling of the DRAM cell in DDR5 renders it more susceptible to data retention failures.…”

Section: Discussion: Rowhammer On Ddr5 Drammentioning

confidence: 99%

Rowhammer Attacks in Dynamic Random-Access Memory and Defense Methods

Kim,

Park,

Yeo

et al. 2024

Sensors

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This paper provides a comprehensive overview of the security vulnerability known as rowhammer in Dynamic Random-Access Memory (DRAM). While DRAM offers many desirable advantages, including low latency, high density, and cost-effectiveness, rowhammer vulnerability, first identified in 2014, poses a significant threat to computing systems. Rowhammer attacks involve repetitive access to specific DRAM rows, which can cause bit flips in neighboring rows, potentially compromising system credentials, integrity, and availability. The paper discusses the various stages of rowhammer attacks, explores existing attack techniques, and examines defense strategies. It also emphasizes the importance of understanding DRAM organization and the associated security challenges.

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Section: Discussion: Rowhammer On Ddr5 Drammentioning

confidence: 99%

Rowhammer Attacks in Dynamic Random-Access Memory and Defense Methods

Kim,

Park,

Yeo

et al. 2024

Sensors

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“…Mithril shows lower or competitive area overhead in terms of KB per bank, reaching 0.024mm 2 at 6.25K RH T H . It is 1% of a single DDR5 chip [27] when multiplied 32× to cover the 32 banks per chip.…”

Section: Comparison With the Prior Workmentioning

confidence: 99%

Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh

Kim¹,

Park²,

Park³

et al. 2021

Preprint

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Since its public introduction in the mid-2010s, the Row Hammer (RH) phenomenon has drawn significant attention from the research community due to its security implications. Although many RH-protection schemes have been proposed by processor vendors, DRAM manufacturers, and academia, they still have shortcomings. Solutions implemented in the memory controller (MC) pay an increasingly higher cost due to their conservative design for the worst case in terms of the number of DRAM banks and RH threshold to support. Meanwhile, the DRAM-side implementation has a limited time margin for RH protection measures or requires extensive modifications to the standard DRAM interface.Recently, a new command for RH protection has been introduced in the DDR5/LPDDR5 standards, called refresh management (RFM). RFM enables the separation of the tasks for RH protection to both MC and DRAM. It does so by having the former generate an RFM command at a specific activation frequency, and the latter take proper RH protection measures within a given time window. Although promising, no existing study presents and analyzes RFM-based solutions for RH protection. In this paper, we propose Mithril, the first RFM interface-compatible, DRAM-MC cooperative RH protection scheme providing deterministic protection guarantees. Mithril has minimal energy overheads for common use cases without adversarial memory access patterns. We also introduce Mithril+, an extension to provide minimal performance overheads at the expense of a tiny modification to the MC while utilizing an existing DRAM command.

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“…For quarter-rate operation in the memory interface, quadrature clocks are generated by dividing high-speed differential clocks [4][5][6]. Skew between the quadrature clocks at the destination is introduced due to noise, mismatch and process, voltage, and temperature (PVT) variation of the clock distribution.…”

Section: Introductionmentioning

confidence: 99%

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces

Park

Lee

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, a quadrature signal corrector (QSC) with high accuracy and fast correction for memory interfaces is presented. An adaptive delay gain controller in the QSC adjusts each delay gain of four digitally controlled delay lines (DCDLs) separately depending on skew between the quadrature clocks, resulting in short correction time together with low residual skew. To validate the effectiveness of our QSC in memory interfaces, a quarter-rate single-ended 1-tap decision feedback equalizer (DFE) with the QSC was fabricated in a 65nm CMOS process. Using the adaptive delay gain controller, the QSC reduced the skew between the 3 GHz quadrature clocks from a maximum of 21.2 ps to 0.8 ps while correction time was reduced by a factor of 3.9 compared to that without using the adaptive delay gain controller. At 12 Gb/s, the DFE using our QSC achieved a BER of 10 −12 with an eye width of 140 mUI when the input clock skew is 13.2 ps.

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23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme

Cited by 17 publications

References 2 publications

Rowhammer Attacks in Dynamic Random-Access Memory and Defense Methods

Rowhammer Attacks in Dynamic Random-Access Memory and Defense Methods

Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces

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