“…As the memory bandwidth required for mobile devices and computing systems for big data processing such as cloud computing and artificial intelligence (AI) increases, the operating frequency of the memory I/O link is continuously increasing. Recent high-speed DRAMS [1,2,5,6,7,8,9,10] and memory controllers [3,4] operating above multi-Gbps demand very precise 50% on-chip duty-cycle clocks to improve timing margins. However, the clock duty-cycle of a memory system is distorted by impedance mismatches, dispersion and crosstalk noise that occur in memory interface channels operating above multiple GHz.…”