2017 IEEE International Solid-State Circuits Conference (ISSCC) 2017
DOI: 10.1109/isscc.2017.7870429
|View full text |Cite
|
Sign up to set email alerts
|

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
4
0

Year Published

2017
2017
2023
2023

Publication Types

Select...
4
3

Relationship

0
7

Authors

Journals

citations
Cited by 24 publications
(4 citation statements)
references
References 2 publications
0
4
0
Order By: Relevance
“…As a result of the analysis, it was confirmed that the greater the rainfall, the greater the difference in power generation. Lee et al (2019) analyzed the power generation effect of an unmanned washing robot for artificial washing in April 2019 (five times), focusing on a photovoltaic module (158 kW) installed on the roof of a building [22]. As a result, it was confirmed that the amount of power generated in the washing section was improved.…”
Section: Cleaning Effect Of Photovoltaic Modulementioning
confidence: 95%
“…As a result of the analysis, it was confirmed that the greater the rainfall, the greater the difference in power generation. Lee et al (2019) analyzed the power generation effect of an unmanned washing robot for artificial washing in April 2019 (five times), focusing on a photovoltaic module (158 kW) installed on the roof of a building [22]. As a result, it was confirmed that the amount of power generated in the washing section was improved.…”
Section: Cleaning Effect Of Photovoltaic Modulementioning
confidence: 95%
“…As the memory bandwidth required for mobile devices and computing systems for big data processing such as cloud computing and artificial intelligence (AI) increases, the operating frequency of the memory I/O link is continuously increasing. Recent high-speed DRAMS [1,2,5,6,7,8,9,10] and memory controllers [3,4] operating above multi-Gbps demand very precise 50% on-chip duty-cycle clocks to improve timing margins. However, the clock duty-cycle of a memory system is distorted by impedance mismatches, dispersion and crosstalk noise that occur in memory interface channels operating above multiple GHz.…”
Section: Introductionmentioning
confidence: 99%
“…Simulated linear duty cycle correction capability of the proposed PFDE according to the V ctrl voltage at 3.4 GHz Layout of the proposed full-swing DCC core IEICE Electronics Express, Vol 16,. No.19,[1][2][3][4][5] …”
mentioning
confidence: 99%
“…So if the duty cycle of the DQS is distorted, it reduces the sampling margins of even and odd data. Since the duty cycle distortion is caused by both of the memory controller and the DRAM, most memory controllers use the duty cycle correction circuit and better transistor technology when compared with transistors of the DRAM process to provide high-quality DQS signals [2].…”
mentioning
confidence: 99%