26.1%‐efficient POLO‐IBC cells: Quantification of electrical and optical loss mechanisms

Abstract

We present experimental results for interdigitated back contacted (IBC) solar cells with passivating POLO contacts for both polarities with a nominal intrinsic poly‐Si region between them. We reach efficiencies of 26.1% and 24.9% on a 1.3 Ω cm and 80 Ω cm p‐type FZ wafer and 24.6% on a 2 Ω cm n‐type Cz wafer, respectively. The initially measured implied efficiency potentials of the cells after passivating the surfaces are very similar, namely, 26.8%, 26.8%, and 26.4%, respectively. We attribute the difference between the efficiency potential and the final current‐voltage measurement to degradation, perimeter, and series and shunt resistance losses, which we quantify by lifetime measurements. With these measurements in combination with a finite element simulation, we determine the surface recombination velocity in the nominal intrinsic poly‐Si region to be in the range from 13 to 21 cm s−1. Using the same approach, we analyze the increase of the front surface recombination velocity during cell processing from 2 to 10 cm s−1 for the 1.3 Ω cm and from 0.5 to 2.3 cm s−1 for the 80 Ω cm. This leads to the fact that cells fabricated on lowly doped bulk material are more vulnerable to a process‐induced degradation of the surface passivation quality. We further determine the theoretical limits of the cells by firstly idealizing the recombination (28% for 1.3 Ω cm and 28.2% for 80 Ω cm) and secondly also idealizing the optics of the solar cells (29.4% and 29.5%).

Separating the two polarities of the POLO contacts of an 26.1%-efficient IBC solar cell

“…The discrepancy between the simulated efficiency of 14.9% and the actual measured efficiency of the cell of 26.1% shows that the S eff value in the cell differs from that on the test structures. The simulations of the 26.1%-efficient cell 40 indicates that the passivation quality in the intrinsic gap regions is between S eff of 15 and 20 cm/s.…”

“…All the other simulation parameters for the description of our cell can be found elsewhere 40 . The simulation shows that the iPOLO junctions with a width of d gap = 30 µm, covers 13.3% of the rear side area and limits the efficiency potential to 14.9%.…”

Passivating contacts for crystalline silicon solar cells

“…19 Following shortly after this, an all poly-Si contacted IBC device was also demonstrated with a PCE of 26.1%, the highest efficiency achieved for a solar cell with both n + and p + poly-Si contacts. 71 The early 1990s saw the development of a low temperature (≤ 200 o C) alternative passivating heterocontact utilizing a stack of intrinsic and doped hydrogenated amorphous silicon (a-Si:H) layers, now known as the silicon heterojunction (SHJ) contact (see Box 2). This structure was inherited from earlier research on a-Si:H/poly-Si tandem cells, 72 and the known surface passivation of c-Si by thin films of a-Si:H. 73 Work on SHJ cells was pioneered by Sanyo (later acquired by Panasonic) and trademarked as the 'Heterojunction with Intrinsic Thin-Layer' or HIT cell.…”

“…contact devices, open data points represent heavily doped, directly metallised contacts, while circles indicate both sides contacted designs, and diamonds IBC designs. 12,[15][16][17][18][19][20][21]35,69,71,81,127,128,130, The red open triangles represent Sunpower devices fabricated prior to their explicitly mentioning the use of passivating contacts in the device structure. Record efficiencies of large area industrial PERC cells (open circles, solid line) are approaching the efficiency ceiling of this device design, foreshadowing a shift in production towards passivating contact cell architectures.…”

“…b, FF vs. Voc for the cell types in a for which data is available. [15][16][17][18][19]21,35,69,71,81,127,128,130,[148][149][150][151][152][153][154][155][156][157]160,161,163,164,[169][170][171][172][173][175][176][177][177][178][179][180][181][182][183][184] For reference the Voc for the optimum c-Si cell efficiency is represented in the vertical hatched line, 4 In practice, Fermi level pinning dampens this effect, often resulting in the depletion of charge carriers from the surface (c). To improve the selectivity of these contacts, either the width (W) of the barrier (ΦB) has to be narrowed to allow for tunneling process to occur (purple arrow), as in the heavy doping approach (d), or the Fermi level has to be 'de-pinned' (by applying a passivating interlayer, represented in white in e), such that the semiconductor's surface...…”