27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power

Prabhat, Pranay; Labbe, Benoît; Knight, Graham; Savanth, Anand; Svedas, Jonas; Walker, Matthew J.; Jeloka, Supreet; Fan, Philex Ming-Yan; García‐Redondo, Fernando; Achuthan, Thanusree; Myers, James

doi:10.1109/isscc19947.2020.9063136

Cited by 22 publications

(8 citation statements)

References 3 publications

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“…In addition, power gating with frequency scaling [23] and body biasing (TEI-BB) [24], [25] have been presented, which exploit the TEI-benefit to further reduce the power consumption of ULV SoCs. Most recently, the efficacies of the TEI-VS and TEI-BB have been verified in fabricated chips in [26]- [28].…”

Section: B Tei-aware Low-power Techniquesmentioning

confidence: 99%

“…Due to the TEI phenomenon, ULV operating circuits have the opportunity to improve power consumption and performance, and a number of researchers have tried to exploit these ideas for dynamic power and thermal management methods [17]- [25]. Moreover, recent research has confirmed the effectiveness of these methods on fabricated System on Chips (SoCs) [26]- [28].…”

mentioning

confidence: 99%

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Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Han

Lee

et al. 2021

IEEE Internet Things J.

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Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 • C and 0.44 V at 80 • C while continuing to operate at a target 50-MHz clock frequency.

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Section: B Tei-aware Low-power Techniquesmentioning

confidence: 99%

mentioning

confidence: 99%

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Han

Lee

et al. 2021

IEEE Internet Things J.

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“…2 Although these designs contain an application specific analog frontend (AFE) their digital NN accelerators could potentially be used for other applications in a smart wakeup scenario. 3 For fair comparison with our digital-only CWU, only the power consumption of the included general-purpose classification logic is considered. 4 Exact area breakdown is not available thus we estimated the area of the classification logic from the chip micrograph.…”

Section: B Cognitive Wake-up Unitmentioning

confidence: 99%

“…2 2 FLOPSs = 1 FMAC on MatMul benchmark unless differently specified. 3 8-bit ML Workloads. 4 Execution from SRAM.…”

Section: Comparison With Soamentioning

confidence: 99%

“…Recent research on ULP MCUs design focused on main building blocks, such as memories [1], standard cells [2] and embedded power management [3]. On the other hand, while more traditional low-end IoT end-nodes are targeted to low-bandwidth sensors (e.g., temperature and pressure) and require limited compute capabilities, an increasing number of applications rely on embedding much more intelligence at the edge.…”

Section: Introductionmentioning

confidence: 99%

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Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

Rossi,

Conti,

Eggimann

et al. 2021

Preprint

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Internet-of-Things requires end-nodes with ultra-low-power always-on capability for a long battery lifetime, as well as high performance, energy efficiency, and extreme flexibility to deal with complex and fast-evolving near-sensor analytics algorithms (NSAAs). We present Vega, an IoT end-node SoC capable of scaling from a 1.7 µW fully retentive cognitive sleep mode up to 32.2 GOPS (@ 49.4 mW) peak performance on NSAAs, including mobile DNN inference, exploiting 1.6 MB of state-retentive SRAM, and 4 MB of non-volatile MRAM. To meet the performance and flexibility requirements of NSAAs, the SoC features 10 RISC-V cores: one core for SoC and IO management and a 9-cores cluster supporting multi-precision SIMD integer and floating-point computation. Vega achieves SoAleading efficiency of 615 GOPS/W on 8-bit INT computation (boosted to 1.3TOPS/W for 8-bit DNN inference with hardware acceleration). On floating-point (FP) compuation, it achieves SoAleading efficiency of 79 and 129 GFLOPS/W on 32-and 16bit FP, respectively. Two programmable machine-learning (ML) accelerators boost energy efficiency in cognitive sleep and active states, respectively.

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DSC-TRCP: Dynamically Self-calibrating Tunable Replica Critical Paths Timing Monitoring for Variation Resilient Circuits with Low Cost & Large Power/Frequency Gain

Shen

Shan

et al. 2022

2022 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power

Cited by 22 publications

References 3 publications

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

DSC-TRCP: Dynamically Self-calibrating Tunable Replica Critical Paths Timing Monitoring for Variation Resilient Circuits with Low Cost & Large Power/Frequency Gain

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