27.3: 1.2 Gbps GDDR3 Physical Layer for 3D AMOLED Panel

Abstract

A 1.2-Gbps GDDR3 physical layer (PHY) circuit for flat panel displays is presented. To reduce the channel skew and to make the clock robust against power supply noise, an automatic skewcalibration algorithm and a coarse lock detector with hysteresis are proposed. The GDDR3 PHY has been integrated in a timing controller chip fabricated in standard 0.13-µm CMOS process.