28.8 Multi-Modal Peripheral Nerve Active Probe and Microstimulator with On-Chip Dual-Coil Power/Data Transmission and 64 2<sup>nd</sup>-Order Opamp-Less ΔΣ ADCs

ElAnsary, Maged; Xu, Jianxiong; Filho, Jose Sales; Dutta, Gairik; Long, Liam; Shoukry, Aly; Tejeiro, Camilo; Tang, Chenxi; Kilinc, Enver G.; Joshi, Jaimin; Sabetian, Parisa; Unger, Samantha; Zariffa, José; Yoo, Paul B.; Genov, Roman

doi:10.1109/isscc42613.2021.9365856

Cited by 19 publications

(4 citation statements)

References 12 publications

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“…TBioCAS 2019 [45] JSSC 2020 [18] ISSCC 2020 [46] ISSCC 2020 [27] ISSCC 2021 [22] JSSC 2021 [47] JSSC 2022 [2] ISSCC 2022 [48] This Work e Calculated by including the 20dB SNDR improvement. f For 10 kHz chopping frequency.…”

Section: Referencementioning

confidence: 99%

“…Considering that the integrator has memory effect, the integration of a distorted value disturbs several consecutive quantized data, degrading the overall DR. To prevent this, the sampling rate and loop dynamics of a CT-∆Σ ADC must be over-designed to accommodate quantization of large-amplitude sharp SAs, which leads to an excessive power consumption. A CT-∆Σ ADC with adaptively varying sampling rate is presented in [22] to combat the issue; nevertheless, the required long settling time makes this technique ineffective.…”

Section: Introductionmentioning

confidence: 99%

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A CMOS BD-BCI: Neural Recorder With Two-Step Time-Domain Quantizer and Multipolar Stimulator With Dual-Mode Charge Balancing

Danesh,

Pu,

Safiallah

et al. 2024

IEEE Trans. Biomed. Circuits Syst.

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This work presents a bi-directional brain-computer interface (BD-BCI) including a high-dynamic-range (HDR) twostep time-domain neural acquisition (TTNA) system and a highvoltage (HV) multipolar neural stimulation system incorporating dual-mode time-based charge balancing (DTCB) technique. The proposed TTNA includes four independent recording modules that can sense microvolt neural signals while tolerating large stimulation artifacts. In addition, it exhibits an integrated inputreferred noise of 2.3 µVrms from 0.1-to 250-Hz and can handle a linear input-signal swing of up to 340 mV PP . The multipolar stimulator is composed of four standalone stimulators each with a maximum current of up to 14 mA (±20-V of voltage compliance) and 8-bit resolution. An inter-channel interference cancellation circuitry is introduced to preserve the accuracy and effectiveness of the DTCB method in the multipolar-stimulation configuration. Fabricated in an HV 180-nm CMOS technology, the BD-BCI chipset undergoes extensive in-vitro and in-vivo evaluations. The recording system achieves a measured SNDR, SFDR, and CMRR of 84.8 dB, 89.6 dB, and >105 dB, respectively. The measurement results verify that the stimulation system is capable of performing high-precision charge balancing with ±2 mV and ±7.5 mV accuracy in the interpulse-bounded time-based charge balancing (TCB) and artifactless TCB modes, respectively.

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Section: Referencementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A CMOS BD-BCI: Neural Recorder With Two-Step Time-Domain Quantizer and Multipolar Stimulator With Dual-Mode Charge Balancing

Danesh,

Pu,

Safiallah

et al. 2024

IEEE Trans. Biomed. Circuits Syst.

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“…The studies by [9], [10] incorporate a passive second-order loop filter in the delta-sigma ADC, mitigating the limitations of the power-intensive integrator. As illustrated in Fig.…”

Section: The State Of Art Neural Adcmentioning

confidence: 99%

MEDSA: A Memristive-passive Delta-Sigma ADC Circuit for Detecting Neural Signals

You,

Xu,

Amirsoleimani

et al. 2023

Preprint

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In this study, we present an analog-to-digital converter (ADC) optimized for implantable neural interfaces. The proposed ADC integrates a series of memristors in both the input and feedback Digital-to-Analog Converter (DAC), significantly boosting the input impedance and making it suitable for neural interfaces. A defining feature of the ADC is the ability of the memristor resistance to adapt to various conditions such as large DC offset, motion, and stimulation artifacts. The model was simulated using 65nm MOSFET technology along with a physical memristor model, yielding an impressive signal-to-noiseand-distortion ratio (SNDR) of 62.7dB and a substantial Nyquist sampling rate of 50kHz. Power consumption is remarkably low, with less than nW for integrators, 5µW for the comparator, and 0.45 µW for the feedback DAC -a key requirement for neural interfaces implanted in the brain. The ADC demonstrates strong resilience against component mismatch, maintaining circuit stability even in variable conditions. Through its ability to adjust input resistance, the ADC can enhance its SNDR. This adaptive and robust ADC design shows promising potential for implantable neural interface applications.

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“…However, when a given OSR is limited in system design, there is a fatal disadvantage in that high-resolution ADC design is limited due to the limitation of kT/C noise [53][54][55]. Therefore, research on a high-resolution ADC structure less affected by kT/C noise is clearly needed.…”

Section: Noise Constraints For High Resolution Adcsmentioning

confidence: 99%

Discrete-time delta-sigma analog-to-digital converter using VCO-based quantizer for IoT applications

An¹

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Low-power systems are essential for Internet-of-Things (IoT) applications powered by harvested energy or batteries, such as wearable devices, structural health monitoring, industrial process monitoring, and personal health monitoring. Analog to digital converter (ADC) is an essential part of the IoT sensor interface and communication system that receives analog signals such as radio waves, light, sound, and biological signals. Depending on the purpose, the ADC is designed for the targets of low voltage operation, dynamic voltage scaling, and high resolution. The technology and supply voltage scaling caused by technological advances reduce voltage headroom and signal power, which makes it challenging to achieve high performance in analog circuit design. A voltagecontrolled oscillator (VCO) based ADC that processes analog information in the time domain can be desirable for technology and supply voltage scaling.However, the conventional VCO-based ADCs present challenges such as dynamic voltage scaling, process variation, narrow input range, and discretetime operation. For high-resolution ADC design, ΔΣ ADC began regaining its popularity as a research topic for high resolution. The discrete-time (DT) ΔΣ ADC effectively reduces two primary noise sources. They are quantization noise and kT/C noise. kT/C noise is more prominent than the quantization noise in high-resolution ADC. kT/C noise is inversely proportional to sampling capacitance and oversampling ratio (OSR). Therefore, high OSR and large capacitance reduce the kT/C noise. Generally, high OSR is preferred to the large capacitance, for the area and power efficiency. However, high-resolution ADC designs are limited in environments where a high OSR cannot be applied.

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28.8 Multi-Modal Peripheral Nerve Active Probe and Microstimulator with On-Chip Dual-Coil Power/Data Transmission and 64 2^nd-Order Opamp-Less ΔΣ ADCs

Cited by 19 publications

References 12 publications

A CMOS BD-BCI: Neural Recorder With Two-Step Time-Domain Quantizer and Multipolar Stimulator With Dual-Mode Charge Balancing

A CMOS BD-BCI: Neural Recorder With Two-Step Time-Domain Quantizer and Multipolar Stimulator With Dual-Mode Charge Balancing

MEDSA: A Memristive-passive Delta-Sigma ADC Circuit for Detecting Neural Signals

Discrete-time delta-sigma analog-to-digital converter using VCO-based quantizer for IoT applications

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28.8 Multi-Modal Peripheral Nerve Active Probe and Microstimulator with On-Chip Dual-Coil Power/Data Transmission and 64 2nd-Order Opamp-Less ΔΣ ADCs

Cited by 19 publications

References 12 publications

A CMOS BD-BCI: Neural Recorder With Two-Step Time-Domain Quantizer and Multipolar Stimulator With Dual-Mode Charge Balancing

A CMOS BD-BCI: Neural Recorder With Two-Step Time-Domain Quantizer and Multipolar Stimulator With Dual-Mode Charge Balancing

MEDSA: A Memristive-passive Delta-Sigma ADC Circuit for Detecting Neural Signals

Discrete-time delta-sigma analog-to-digital converter using VCO-based quantizer for IoT applications

Contact Info

Product

Resources

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28.8 Multi-Modal Peripheral Nerve Active Probe and Microstimulator with On-Chip Dual-Coil Power/Data Transmission and 64 2^nd-Order Opamp-Less ΔΣ ADCs