28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures

Esfeh, Babak Kazemi; Planes, N.; Haond, M.; Raskin, Jean‐Pierre; Flandre, Denis; Kilchytska, Valeriya

doi:10.1016/j.sse.2019.03.039

Cited by 22 publications

(9 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, depending on the target application, either high-frequency/high-current, or baseband (high-precision, gain), one would choose device with strain or without, respectively. Finally, Figure 2d demonstrates effect of temperature down to 4.2 K on gm/Id versus Id/(W/L) plot [62,64]. Temperature lowering is seen beneficial both in weak inversion (due to subthreshold slope improvement) and in strong inversion (due to mobility improvement), and thus for both base-band and high-frequency applications.…”

Section: Dc-based Techniques (Or Techniques Based On Static Measmentioning

confidence: 94%

“…(c) gm/Id as a function of Id/(W/L) in FinFETs with and without strain [58]. (d) gm/Id as a function of Id/(W/L) in FDSOI MOSFET at different temperatures[62,64].…”

mentioning

confidence: 99%

“…gm -Av metric application in the case of (a) various NW MOSFETs[56], (b) FDSOI MOSFETs at room and cryogenic temperatures[62,64]; (c) UTBB SOI MOSFETs at different back-gate biases[57]; (d) UTBB SOI MOSFETs operating in ADG and QDG regimes[49,50].…”

mentioning

confidence: 99%

See 2 more Smart Citations

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Kilchytska

Makovejev²,

Esfeh

et al. 2021

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

This review paper assesses the main approaches in the electrical characterization of advanced MOSFETs towards their future analog and RF applications. Those approaches are shown to be different from the traditionally used ones for the assessment of the device perspectives for digital applications. Based on the original research realized by our group over the last years, advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as Fully Depleted Silicon-on-Insulator (FDSOI), FinFETs and NanoWires (NW) in a wide temperature range (from cryogenic, 4 K up to 250°C). A wide frequency band characterization (from DC up to hundred GHz range) will be positioned as a key element enabling a fair device assessment towards analog and RF applications. Importance of the "extrinsic" parasitic elements in the advanced devices is enormous, sometimes even dominating the device performance. Therefrom arises the need for a proper separate extraction and discussion of "intrinsic" versus "extrinsic" parameters.

show abstract

Section: Dc-based Techniques (Or Techniques Based On Static Measmentioning

confidence: 94%

“…(c) gm/Id as a function of Id/(W/L) in FinFETs with and without strain [58]. (d) gm/Id as a function of Id/(W/L) in FDSOI MOSFET at different temperatures[62,64].…”

mentioning

confidence: 99%

See 1 more Smart Citation

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Kilchytska

Makovejev²,

Esfeh

et al. 2021

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…The ZTC bias point therefore enables the extraction of the small-signal parameters associated to the B-G and substrate nodes without any dependency on the SH effects. As the ZTC bias point is not specific to this technology [16]- [20] and has been experimentally verified down to cryogenic temperatures [21]- [22], the proposed methodology can be widely applied. By taking the real and imaginary parts of (1), we can derive the equations describing the dynamic SH effect on gd(f) and Cdd(f):…”

Section: A Advantage Of Ztc Bias For Unambiguous Extractionmentioning

confidence: 99%

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

Nyssens

Rack

Halder

et al. 2021

IEEE Electron Device Lett.

Self Cite

View full text Add to dashboard Cite

This paper proposes an original approach to separately characterize self-heating and substrate effects in Fully-Depleted Silicon-on-Insulator (FD-SOI) devices. As both dynamic self-heating and drain to source coupling through the back-gate and substrate of an FD-SOI MOSFET induce a frequency transition in the Y-parameters in a common frequency range, it is crucial to properly separate them for further modeling. The proposed novel method is based on the extraction of the back-gate and substrate networks from the S-parameters measured at the zerotemperature coefficient bias. It enables the accurate and unambiguous extraction of thermal impedance for different biases, thus providing the extraction of the device thermal resistance and capacitance for different power levels from S-parameters measurements.

show abstract

“…DIBL is important because it causes drain current that depends on V d | | during saturation-mode operation and so can affect the operation of analog circuits. Interestingly, some studies have shown increases in DIBL at cryogenic temperatures [5][6][7][8][9] while others have not, [10][11][12][13][14] and this discrepancy has not been explained. In the present study, V t values were investigated at cryogenic temperatures with a focus on the impact of source and drain extension design on these values.…”

mentioning

confidence: 96%

Importance of source and drain extension design in cryogenic MOSFET operation: causes of unexpected threshold voltage increases

Inaba

Asai

Hattori

et al. 2022

Appl. Phys. Express

View full text Add to dashboard Cite

Increased threshold voltages have been observed during linear-mode operation of short-channel bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) employing shallow source and drain extension technology at cryogenic temperatures. These increases were suppressed during saturation-mode operation, which resulted in the increase of a threshold voltage mismatch between linear- and saturation-modes as if drain-induced barrier lowering occurred. Numerical simulations revealed that these increases originate from enhanced depletion in the extension region and subsequent increases in channel resistance at cryogenic temperatures. These data suggest that shallow extensions should be designed more carefully in the case of MOSFETs intended for cryogenic operation.

show abstract

28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures

Cited by 22 publications

References 19 publications

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

Importance of source and drain extension design in cryogenic MOSFET operation: causes of unexpected threshold voltage increases

Contact Info

Product

Resources

About

28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures

Cited by 22 publications

References 19 publications

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

Importance of source and drain extension design in cryogenic MOSFET operation: causes of unexpected threshold voltage increases

Contact Info

Product

Resources

About

28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures