29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS

High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

“…Only in bipolar technology, significant faster multiplexing is achieved (Schuh et al, 2016). Simulation results are comparable to the serializer in Cao et al (2017) but the speed is achieved in the 28 nm technology node and in static CMOS logic (modified by resistive coupling) instead of CML. The main advantages of this circuit are the high output data rates up to 64 Gbit s −1 , the static CMOS compatibility concerning supply voltages and the requirement of only one differential clock phase for all frequency domains.…”

“…Finally, FD-SOI Figure 1. Optical coherent transmission system (Huang et al, 2015;Cao et al, 2017;Laperle and O'Sullivan, 2014 technology allows for flip well transistors due to a buried oxide (BOX) layer of 25 nm below the thin channel of 7 nm, meaning an NMOS transistor is built on an n-well and a PMOS transistor is build on a p-well layer separated by the BOX. This specific feature enables more efficient forward body biasing within a much larger voltage range compared to bulk processes which is an advantage owing to strong threshold voltage control and faster switching processes.…”

“…To provide several channels with very high data rates of tens of Gbit s −1 , multiplexers (MUXs) are required for serialization (Huang et al, 2015;Cao et al, 2017). Here, a fullydifferential serializer including a 19 channel 16 : 1 MUX for output data rates up to 64 Gbit s −1 per channel as well as a low skew (∼ 8.8 ps) two-phase differential frequency divider and clock distribution network is presented.…”

Challenges and Trade-offs in Real-Time Implementation of DSP for Coherent Transmission

“…But the limited electrical chip-tochip bandwidth is a serious impediment to system integration of complex real-time implementations. Thanks to time-interleaved successive-approximation (SAR) ADC architectures and their ability to scale with (digital) CMOS technology, CMOS ADCs can reach high sampling rates [6] enabling on-chip DSP-ADC integration [7]. While on-chip integration greatly enhances the signal bandwidth between different units, the noise injected by high-speed switching logic circuits into sensitive analog portions, like ADC samplers, presents a design challenge.…”

“…While digital subcarrier multiplexing offers one path to limiting symbol rate at the system level [3,13], choice of oversampling is a trade-off available during receiver implementation. An oversampling of 2 samples per symbol (SPS) has been common, since this choice relaxes ADC requirements and enables powerful equalization schemes [7]. If the oversampling rate is reduced, penalties due to aliasing and reduced filter bandwidths increase.…”