290 psec I&lt;sup&gt;2&lt;/sup&gt;L circuits with five-fold self-alignment

Nakamura, Tohru; Nakazato, Kazuhiko; Miyazaki, Takao; Ogirima, Masahiko; Okabe, T.; Nagata, M.

doi:10.1109/iedm.1982.190386

Cited by 3 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Optimum performance at the highest achievable current level was achieved by ensuring that the depletion and stored charge components in the vicinity of the NpN base are equal. The predicted gate delay of 34 ps is 8.5 times lower than the reported experimental value of 290 ps for 3 micron pure Si I L gates [14], which clearly demonstrates the potential of SiGe I L. In addition, there is undoubtedly scope for improving on the gate delay by scaling the device geometry and further optimising the gate layout.…”

Section: A Self-aligned Sige I L Technologymentioning

confidence: 69%

“…Even further benefits would be obtained if self-aligned fabrication schemes were used to reduce depletion charge and eliminate the excess charge associated with the extrinsic base rails [4]. Such a strategy has achieved a switching time of 290 ps in a pure Si I L gate [14] at a gate geometry of 3 m and one for SiGe I L is presented in the next section.…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Analysis of Si:Ge heterojunction integrated injection logic (I/sup 2/L) structures using a stored charge model

Wainwright

Hall

Ashburn

et al. 1998

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

A quasi-two-dimensional stored charge model is developed as an aid to the optimization of SiGe integrated injection logic (I 2 L) circuits. The model is structure-based and partitions the stored charge between the different regions of the I 2 L gate. Both the NpN switching transistor and the PNp load transistor are correctly modeled and the effects of series resistances on the gate operation are taken into account. The model is applied to surface-fed and substrate-fed variants of SiGe I 2 L and the Ge and doping concentrations varied to determine the important tradeoffs in the gate design. At low injector currents, the substrate-fed variant is found to be faster because of lower values of critical depletion capacitances. At high injector currents, the performance of both variants is limited by series resistances, particularly in the NpN emitter layer. The inclusion of 16% Ge in the substrate-fed I 2 L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100 ps should be achievable in SiGe I 2 L even at a geometry of 3 m. The model is applied to a realistic, self-aligned structure and a delay of 34 ps is predicted. It is expected that this performance can be improved with a fully optimized, scaled structure. NOMENCLATURE N-type Si doping concentration in the substrate (used exclusively in C-I L). N-type Si doping concentration in the switch emitter (used exclusively in C-I L). N-type Si doping concentration in the injector base

show abstract

Section: A Self-aligned Sige I L Technologymentioning

confidence: 69%

Section: Discussionmentioning

confidence: 99%