2D materials: roadmap to CMOS integration

Huyghebaert, Cedric; Schram, T.; Smets, Quentin; Agarwal, Tarun; Verreck, Devin; Brems, Steven; Phommahaxay, Alain; Chiappe, Daniele; Kazzi, Salim El; Rosa, C. Lockhart de la; Arutchelvan, Goutham; Cott, Daire; Ludwig, Jonathan; Gaur, Anurag; Sutar, Surajit; Leonhardt, Alessandra; Marinov, Daniil; Lin, Dennis; Caymax, Matty; Asselberghs, Inge; Pourtois, Geoffrey; Radu, Iuliana

doi:10.1109/iedm.2018.8614679

Cited by 78 publications

(72 citation statements)

References 32 publications

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“…This thereby vastly expands the inventory of ferroelectrics and 2D semiconductors for functional heterostructures that can not only provide customizable functionalities but also be fabricated on large scale, leading to a new heterogeneous platform fueling future advances of semiconductor technology. [36,37] Herein, we provide a timely account of recent advances in emerging 2D semiconductor/ferroelectric transistorstructured devices (Figure 1), covering their device configurations, operation mechanisms and state-of-the-art experimental realizations along with challenges. In Section 2, we discuss heterostructure integration strategies and device construction as well as challenges for device performance improvement.…”

Section: Introductionmentioning

confidence: 99%

Emerging Opportunities for 2D Semiconductor/Ferroelectric Transistor‐Structure Devices

et al. 2021

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Semiconductor technology, which is rapidly evolving, is poised to enter a new era for which revolutionary innovations are needed to address fundamental limitations on material and working principle level. 2D semiconductors inherently holding novel properties at the atomic limit show great promise to tackle challenges imposed by traditional bulk semiconductor materials. Synergistic combination of 2D semiconductors with functional ferroelectrics further offers new working principles, and is expected to deliver massively enhanced device performance for existing complementary metal–oxide–semiconductor (CMOS) technologies and add unprecedented applications for next‐generation electronics. Herein, recent demonstrations of novel device concepts based on 2D semiconductor/ferroelectric heterostructures are critically reviewed covering their working mechanisms, device construction, applications, and challenges. In particular, emerging opportunities of CMOS‐process‐compatible 2D semiconductor/ferroelectric transistor structure devices for the development of a rich variety of applications are discussed, including beyond‐Boltzmann transistors, nonvolatile memories, neuromorphic devices, and reconfigurable nanodevices such as p–n homojunctions and self‐powered photodetectors. It is concluded that 2D semiconductor/ferroelectric heterostructures, as an emergent heterogeneous platform, could drive many more exciting innovations for modern electronics, beyond the capability of ubiquitous silicon systems.

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Section: Introductionmentioning

confidence: 99%

Emerging Opportunities for 2D Semiconductor/Ferroelectric Transistor‐Structure Devices

et al. 2021

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“…[ 30,31 ] Significant research efforts are also underway to develop strategies for compatibility with Si CMOS technologies. [ 32,33 ] Hence, the 2D TMDC family is a very compelling alternative for building solid‐state qubits. Various groups [ 31,34–40 ] have therefore invested efforts (see for example the facilities highlighted in Figure ) to build electrostatically gated quantum dots in 2D TMDCs which could potentially lead to the development of qubits on the same platform.…”

Section: Introductionmentioning

confidence: 99%

Toward Valley‐Coupled Spin Qubits

et al. 2020

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The bid for scalable physical qubits has attracted many possible candidate platforms. In particular, spin‐based qubits in solid‐state form factors are attractive as they could potentially benefit from processes similar to those used for conventional semiconductor processing. However, material control is a significant challenge for solid‐state spin qubits as residual spins from substrate, dielectric, electrodes, or contaminants from processing contribute to spin decoherence. In the recent decade, valleytronics has seen a revival due to the discovery of valley‐coupled spins in monolayer transition metal dichalcogenides. Such valley‐coupled spins are protected by inversion asymmetry and time reversal symmetry and are promising candidates for robust qubits. In this report, the progress toward building such qubits is presented. Following an introduction to the key attractions in fabricating such qubits, an up‐to‐date brief is provided for the status of each key step, highlighting advancements made and/or outstanding work to be done. This report concludes with a perspective on future development highlighting major remaining milestones toward scalable spin‐valley qubits.

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“…There have been extensive efforts invested toward the fabrication of good 1L devices. Interuniversity Microelectronics Centre 17 has recently reported 300 mm wafer scale 1L WS 2 field effect transistors (FETs) with a current density of ∼10 μA/μm and mobility of few cm 2 V –1 s –1 . In addition, Smithe et al 18 showed low electrical variability in CVD-grown 1L MoS 2 despite the presence of bilayers (2Ls) because of small 1L/2L conduction band offsets.…”

Section: Introductionmentioning

confidence: 99%

Improved Current Density and Contact Resistance in Bilayer MoSe₂ Field Effect Transistors by AlO_x Capping

Somvanshi

Ber

Bailey

et al. 2020

ACS Appl. Mater. Interfaces

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Atomically thin semiconductors are of interest for future electronics applications, and much attention has been given to monolayer (1L) sulfides, such as MoS 2 , grown by chemical vapor deposition (CVD). However, reports on the electrical properties of CVD-grown selenides, and MoSe 2 in particular, are scarce. Here, we compare the electrical properties of 1L and bilayer (2L) MoSe 2 grown by CVD and capped by sub-stoichiometric AlO x . The 2L channels exhibit ∼20× lower contact resistance ( R C ) and ∼30× larger current density compared with 1L channels. R C is further reduced by >5× with AlO x capping, which enables improved transistor current density. Overall, 2L AlO x -capped MoSe 2 transistors (with ∼500 nm channel length) achieve improved current density (∼65 μA/μm at V DS = 4 V), a good I on / I off ratio of >10 6 , and an R C of ∼60 kΩ·μm. The weaker performance of 1L devices is due to their sensitivity to processing and ambient. Our results suggest that 2L (or few layers) is preferable to 1L for improved electronic properties in applications that do not require a direct band gap, which is a key finding for future two-dimensional electronics.

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2D materials: roadmap to CMOS integration

Cited by 78 publications

References 32 publications

Emerging Opportunities for 2D Semiconductor/Ferroelectric Transistor‐Structure Devices

Emerging Opportunities for 2D Semiconductor/Ferroelectric Transistor‐Structure Devices

Toward Valley‐Coupled Spin Qubits

Improved Current Density and Contact Resistance in Bilayer MoSe₂ Field Effect Transistors by AlO_x Capping

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2D materials: roadmap to CMOS integration

Cited by 78 publications

References 32 publications

Emerging Opportunities for 2D Semiconductor/Ferroelectric Transistor‐Structure Devices

Emerging Opportunities for 2D Semiconductor/Ferroelectric Transistor‐Structure Devices

Toward Valley‐Coupled Spin Qubits

Improved Current Density and Contact Resistance in Bilayer MoSe2 Field Effect Transistors by AlOx Capping

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Improved Current Density and Contact Resistance in Bilayer MoSe₂ Field Effect Transistors by AlO_x Capping