2D van der Waals Vertical Heterojunction Transistors for Ternary Neural Networks

Abstract

Compared with binary systems, ternary computing systems can utilize fewer devices to realize the same information density. However, most ternary computing systems based on binary CMOS circuits require additional devices to bridge binary processing and ternary computing. Exploring new device architectures for direct ternary processing and computing becomes the key to promoting ternary computing systems. Here, we demonstrated a 2D van der Waals vertical heterojunction transistor (V-HTR) with three flat conductance states, which can be the basic cell in ternary circuits to perform ternary processing and computing, without additional devices. A ternary neural network (TNN) and a ternary inverter were demonstrated based on the V-HTRs. The TNN can eliminate fuzzy data and output only clear data by building a ternary quantization function. By demonstrating both ternary logic and a TNN on the same device architecture, the 2D V-HTR shows potential as a basic hardware unit for future ternary computing systems.