2D-VLIW: An Architecture Based on the Geometry of Computation

Santos, Ricardo; Azevedo, Rodolfo; Araújo, Guido

doi:10.1109/asap.2006.1

Cited by 9 publications

(7 citation statements)

References 17 publications

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“…This, in effect, used the 2D geometry of VLSI technology to create what might be termed a 2D very large instruction word (VLIW). Interestingly, this concept also has been explored by Santos et al [23]. One difference between their respective approaches appears to be that, in TRIPS, each block asynchronously signals its completion to a global controller; in the 2D-VLIW, the block is scheduled (both placement and dispatch) statically and synchronously.…”

Section: Tera-ops Reliable Intelligently Adaptable Processing Systemmentioning

confidence: 95%

“…The designers replace the crossbar Figure 7. Block execution: Processor core tiles and interfaces: R tiles inject register values, E tiles execute block: load, compute, deliver outputs to R-tiles/D-tiles, and branch to G tile [23]. bypass network with a point-to-point, pipelined, 2D mesh routing network.…”

Section: Reconfigurable Architecture Worktationmentioning

confidence: 99%

“…TRIPS tile-level microarchitecture: Processor[s] as an array of tiles: D data cache, E execution tile, I instruction cache, G global control, M memory (scratchpad or L2 cache), N network interface, R register bank[23].…”

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confidence: 99%

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Application-specific Processor Architecture: Then and Now

Cappello

2007

J Sign Process Syst Sign Image Video Technol

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We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago. We then observe that those same design forces now are bearing down on the architects of contemporary general-purpose processors, who consequently are producing general-purpose processors whose architectural features are increasingly similar to those of systolic arrays. We then describe some economic and technological forces that are changing the landscape of architectural research. At base, they are the increasing complexity of technology and applications, the fragmenting of the general-purpose processor market, and the judicious use hardware configurability. We describe a 2D architectural taxonomy, identifying what, we believe, to be a Bsweet spot^for architectural research.

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Section: Tera-ops Reliable Intelligently Adaptable Processing Systemmentioning

confidence: 95%

Section: Reconfigurable Architecture Worktationmentioning

confidence: 99%

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Application-specific Processor Architecture: Then and Now

Cappello

2007

J Sign Process Syst Sign Image Video Technol

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“…It only achieves around 40% utilization for matrix multiplication. Other 2D architectures [4], [37] introduce a more complex, fully connected interconnect network between the register files and PEs. However, for most matrix operations like GEMM, flexible dataflow facilities in the interconnect are an overhead.…”

Section: B Related Workmentioning

confidence: 99%

On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators

Pedram

Gerstlauer

Geijn

2012

2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing

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Abstract-Reducing power consumption and increasing efficiency is a key concern for many applications. How to design highly efficient computing elements while maintaining enough flexibility within a domain of applications is a fundamental question. In this paper, we present how broadcast buses can eliminate the use of power hungry multi-ported register files in the context of data-parallel hardware accelerators for linear algebra operations. We demonstrate an algorithm/architecture co-design for the mapping of different collective communication operations, which are crucial for achieving performance and efficiency in most linear algebra routines, such as GEMM, SYRK and matrix transposition. We compare a broadcast bus based architecture with conventional SIMD, 2D-SIMD and flat register file for these operations in terms of area and energy efficiency. Results show that fast broadcast data movement abilities in a prototypical linear algebra core can achieve up to 75x better power and up to 10x better area efficiency compared to traditional SIMD architectures.

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“…As instruc ¸ões codificadas PBIW são armazenadas em uma I-cache e os padrões obtidos são armazenados na P-cache. A técnica PBIW foi avaliada através de experimentos com os benchmarks MediaBench, SPECint e SPECfp, implementando a codificac ¸ão PBIW sobre uma arquitetura de alto desempenho conhecida como 2D-VLIW [12]. Os resultados revelam que a técnica PBIW produz programas até 81% menores e até 96% mais rápidos que 2D-VLIW além de até 46% menores e até 69% mais rápidos que EPIC [14].…”

Section: Introduc ¸ãOunclassified

PBIW: Uma Codificação de Instruções Alternativa para Arquiteturas de Alto Desempenho

Batistella

Santos

Azevedo

2008

Anais Do IX Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2008)

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Este artigo apresenta a técnica de codificação PBIW. Essa técnica é baseada na fatoração de grupos de operações escalonadas em instruções codificadas e padrões. Uma instrução codificada não contém dados redundantes e é armazenada em uma cache de instruções. Os padrões são armazenados em uma cache de padrões. Foi realizado um estudo de caso desta técnica sobre esquemas de codificação de instruções denominados 2D-VLIW e EPIC em uma arquitetura de alto desempenho chamada 2D-VLIW. A técnica PBIW foi avaliada com os benchmarks MediaBench, SPECint e SPECfp. Os resultados revelam que a técnica PBIW produz programas até 81% menores que 2D-VLIW e até 46% menores que EPIC, além de programas até 96% mais rápidos que 2D-VLIW e até 69% mais rápidos que EPIC.

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2D-VLIW: An Architecture Based on the Geometry of Computation

Cited by 9 publications

References 17 publications

Application-specific Processor Architecture: Then and Now

Application-specific Processor Architecture: Then and Now

On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators

PBIW: Uma Codificação de Instruções Alternativa para Arquiteturas de Alto Desempenho

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