3.125 Gb/s Power Efficient Line Driver with 2-level Pre-emphasis and 2kV HBM ESD Protection

Abstract

The paper presents a power efficient line driver for 3.125 Gb/s operation over FR-4 copper backplannes. The circuit has been implemented in 0.18µm and dissipates 28 mW from 1.8V power supply. Efficient ESD protection has been used that provided 2kV Human Body Model (HBM) reliability.

ESD protection design for I/O libraries in advanced CMOS technologies

“…The results of mixed-mode simulations at 2 kV HBM ESD stress are depicted in Fig. 4-4 [17]. In this figure, Vg_M0 is the gate voltage of ESD transistor M 0 and V pad is the pad voltage at 2 kV HBM ESD stress applied to the I/O pad.…”