3.7 A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier

ElShater, Ahmed; Lee, Calvin Yoji; Venkatachala, Praveen Kumar; Muhlestein, Jason; Leuenberger, Spencer; Sobue, Kazuki; Hamashita, Koichi; Moon, Un-Ku

doi:10.1109/isscc.2019.8662400

Cited by 15 publications

(9 citation statements)

References 1 publication

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“…Both amplifiers achieve stability without making excessive use of t d based compensation. This technique is used in all RAMP based ADCs with an effective number of bits (ENOB) larger than 13 [1]- [3], except [6]. Choosing a small technology node and the inherently smaller t d also helps making the amplifier stable for a fast [7] or accurate ADC.…”

Section: Adc Design Constraintsmentioning

confidence: 99%

“…Recent works use RAMPs as different types of residue amplifiers in pipelined ADCs. The residue amplifiers have a gain of a factor of two [1]- [3], [5], [7], 32 [4] or 64 [6]. A large gain results in a large feedback factor ψ, which enhances stability.…”

Section: Adc Design Constraintsmentioning

confidence: 99%

“…The work of [4] explains the design of fully differential RAMPs and [5] proposes a technique to replace the offset-voltage capacitors by a resistor. Finally, [6] and [7] identified the size of the offset voltage as a key parameter and provide techniques to tune this voltage dynamically. However, to the best of the author's knowledge, there is no intuitive and straightforward way or an automated method for designing RAMPs.…”

Section: Introductionmentioning

confidence: 99%

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Design Approach for Ring Amplifiers

Conrad

Vogelmann

Mokhtar

et al. 2020

IEEE Trans. Circuits Syst. I

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Ring amplifiers are an advantageous new amplifier architecture, but designing them needs to be done in a time consuming process using manual transient simulations. AC based design criteria are of limit usability, because of their large signal operation. This paper presents an alternative design approach for ring amplifiers. A set of cost functions and parameters is developed and the parameters' effect on the amplifier's stability, accuracy and power consumption is explained in detail. The optimization process is derived from a simple ring-amplifier model and a stability criterion. This criterion is analyzed in the context of circuit parameters, design constraints and other ringamplifier designs. A new battery-based self-biased ring-amplifier architecture is introduced and the first stage integrator of a switched-capacitor Delta-Sigma modulator is realized using the described ring-amplifier architecture. The proposed optimization process is successfully performed using 180 nm and 40 nm technology nodes (second node with two supply voltages) and the three designs are analyzed and compared. The optimization process is derived from a basic ring-amplifier model and can be applied to other ring-amplifier structures.

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Section: Adc Design Constraintsmentioning

confidence: 99%

Section: Adc Design Constraintsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design Approach for Ring Amplifiers

Conrad

Vogelmann

Mokhtar

et al. 2020

IEEE Trans. Circuits Syst. I

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“…High SNDR ADCs are widely used in mixed-signal system-on-chip (SoC) in the fields of both the industrial and the consumer applications. The SAR ADC is well known as a high energy efficiency ADC architecture for medium resolution, low or medium speed applications [1,2,3,4,5,6,7]. However, because the resolution of SAR ADC depends on the offset of comparator and the accuracy of capacitor array matching, it is difficult to realize the high resolution ADC in nanoscale CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

“…IEICE Electronics Express, Vol 16,. No.12,[1][2][3][4][5][6] of 84.16 dB at −1.24 dBFS and −4.37 dBFS are achieved, respectively. The measurement results show that linear SNDR responses up to the full scale, and the dynamic range of 85 dB is achieved.…”

mentioning

confidence: 96%

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

Pan

San

2019

IEICE Electron. Express

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A proof-of-concept delta sigma AD modulator using dynamic analog components with simplified operation mode is designed and fabricated in 90 nm CMOS technology. The measurement results of the experimental prototype demonstrate the feasibility of the proposed modulator architecture which can guarantee the reset time for ring-amplifier and relax the speed requirement on the asynchronous SAR quantizer. The peak SNDR of 77.93 dB and SNR of 84.16 dB are achieved while a sinusoid −4 dBFS input is sampled at 14 MS/s with signal bandwidth of 109 kHz. The total analog power consumption of the prototype modulator is 720 µW under the supply voltage of 1.2 V.

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