3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Abstract

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with especial attention to SoC design strategies. Finally, some of the promising technologies for manufacturing 3-D ICs have been outlined.

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

“…The figure is in the same style as Fig. 11; the differences required to support (1) and (2) are highlighted by means of purple and blue outlines, respectively.…”

“…The Coredis control signal allows to bypass all embedded cores of this die. In order to guarantee that the core-level WIR(s) are in a well-defined safe state, two things are required: (1) each test starts with a reset on wrstn, which should bring the WIR(s) in their (safe) functional start-up state [5], and (2) at the core-level, either the wrck or wrstn signals are AND-gated with the Coredis control signal, which keeps the core-level WIR(s) in their start-up state. In the hierarchical set-up with bypassable embedded cores, we distinguish three types of operations: a wrstn reset, followed by resp.…”

“…TSVs are conducting nails which extend out of the back-side of a thinned-down die, enabling the vertical interconnect to another die [27,32]. TSVs are high-density, low-capacitance interconnects compared to traditional wire-bonds, and hence allow for many more interconnections between stacked dies, while operating at higher speeds and consuming less power [1]. TSV-based three-dimensional technologies enable the creation of a new generation of 'super chips' by opening up new architectural opportunities [20,38].…”

Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models

“…Thus, keeping only the most significant coefficients enables us to represent the original data in a lower dimension. Note that in (1) and (2) we use 2 instead of 2 as a scaling factor since just averaging cannot preserve Euclidean distance in the transformed data.…”

“…Three-dimensional (3D) integrated circuit design [1] is an emerging technology that greatly improves transistor integration density and reduces on-chip wire communication latency. It places planar circuit layers in the vertical dimension and connects these layers with a high density and low-latency interface.…”